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The attached patches provides part 6 of an architecture implementation for the Tensilica Xtensa CPU series. Signed-off-by: Chris Zankel <chris@zankel.net> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
38 lines
842 B
C
38 lines
842 B
C
/*
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* include/asm-xtensa/ipcbuf.h
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*
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* The ipc64_perm structure for the Xtensa architecture.
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* Note extra padding because this structure is passed back and forth
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* between kernel and user space.
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*
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* Copyright (C) 2001 - 2005 Tensilica Inc.
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*/
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#ifndef _XTENSA_IPCBUF_H
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#define _XTENSA_IPCBUF_H
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/*
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* Pad space is left for:
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* - 32-bit mode_t and seq
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* - 2 miscellaneous 32-bit values
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*
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* This file is subject to the terms and conditions of the GNU General
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* Public License. See the file "COPYING" in the main directory of
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* this archive for more details.
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*/
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struct ipc64_perm
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{
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__kernel_key_t key;
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__kernel_uid32_t uid;
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__kernel_gid32_t gid;
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__kernel_uid32_t cuid;
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__kernel_gid32_t cgid;
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__kernel_mode_t mode;
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unsigned long seq;
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unsigned long __unused1;
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unsigned long __unused2;
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};
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#endif /* _XTENSA_IPCBUF_H */
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