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fc06b8520b
The dynamic function tracer relys on the macro P6_NOP5 always being an atomic NOP. If for some reason it is changed to be two operations (like a nop2 nop3) it can faults within the kernel when the function tracer modifies the code. This patch adds a comment to note that the P6_NOPs are expected to be atomic. This will hopefully prevent anyone from changing that. Reported-by: Mathieu Desnoyer <mathieu.desnoyers@polymtl.ca> Signed-off-by: Steven Rostedt <rostedt@goodmis.org>
121 lines
3.3 KiB
C
121 lines
3.3 KiB
C
#ifndef _ASM_X86_NOPS_H
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#define _ASM_X86_NOPS_H
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/* Define nops for use with alternative() */
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/* generic versions from gas
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1: nop
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the following instructions are NOT nops in 64-bit mode,
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for 64-bit mode use K8 or P6 nops instead
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2: movl %esi,%esi
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3: leal 0x00(%esi),%esi
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4: leal 0x00(,%esi,1),%esi
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6: leal 0x00000000(%esi),%esi
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7: leal 0x00000000(,%esi,1),%esi
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*/
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#define GENERIC_NOP1 ".byte 0x90\n"
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#define GENERIC_NOP2 ".byte 0x89,0xf6\n"
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#define GENERIC_NOP3 ".byte 0x8d,0x76,0x00\n"
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#define GENERIC_NOP4 ".byte 0x8d,0x74,0x26,0x00\n"
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#define GENERIC_NOP5 GENERIC_NOP1 GENERIC_NOP4
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#define GENERIC_NOP6 ".byte 0x8d,0xb6,0x00,0x00,0x00,0x00\n"
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#define GENERIC_NOP7 ".byte 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00\n"
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#define GENERIC_NOP8 GENERIC_NOP1 GENERIC_NOP7
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/* Opteron 64bit nops
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1: nop
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2: osp nop
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3: osp osp nop
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4: osp osp osp nop
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*/
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#define K8_NOP1 GENERIC_NOP1
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#define K8_NOP2 ".byte 0x66,0x90\n"
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#define K8_NOP3 ".byte 0x66,0x66,0x90\n"
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#define K8_NOP4 ".byte 0x66,0x66,0x66,0x90\n"
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#define K8_NOP5 K8_NOP3 K8_NOP2
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#define K8_NOP6 K8_NOP3 K8_NOP3
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#define K8_NOP7 K8_NOP4 K8_NOP3
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#define K8_NOP8 K8_NOP4 K8_NOP4
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/* K7 nops
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uses eax dependencies (arbitary choice)
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1: nop
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2: movl %eax,%eax
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3: leal (,%eax,1),%eax
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4: leal 0x00(,%eax,1),%eax
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6: leal 0x00000000(%eax),%eax
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7: leal 0x00000000(,%eax,1),%eax
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*/
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#define K7_NOP1 GENERIC_NOP1
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#define K7_NOP2 ".byte 0x8b,0xc0\n"
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#define K7_NOP3 ".byte 0x8d,0x04,0x20\n"
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#define K7_NOP4 ".byte 0x8d,0x44,0x20,0x00\n"
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#define K7_NOP5 K7_NOP4 ASM_NOP1
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#define K7_NOP6 ".byte 0x8d,0x80,0,0,0,0\n"
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#define K7_NOP7 ".byte 0x8D,0x04,0x05,0,0,0,0\n"
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#define K7_NOP8 K7_NOP7 ASM_NOP1
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/* P6 nops
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uses eax dependencies (Intel-recommended choice)
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1: nop
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2: osp nop
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3: nopl (%eax)
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4: nopl 0x00(%eax)
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5: nopl 0x00(%eax,%eax,1)
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6: osp nopl 0x00(%eax,%eax,1)
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7: nopl 0x00000000(%eax)
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8: nopl 0x00000000(%eax,%eax,1)
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Note: All the above are assumed to be a single instruction.
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There is kernel code that depends on this.
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*/
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#define P6_NOP1 GENERIC_NOP1
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#define P6_NOP2 ".byte 0x66,0x90\n"
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#define P6_NOP3 ".byte 0x0f,0x1f,0x00\n"
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#define P6_NOP4 ".byte 0x0f,0x1f,0x40,0\n"
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#define P6_NOP5 ".byte 0x0f,0x1f,0x44,0x00,0\n"
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#define P6_NOP6 ".byte 0x66,0x0f,0x1f,0x44,0x00,0\n"
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#define P6_NOP7 ".byte 0x0f,0x1f,0x80,0,0,0,0\n"
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#define P6_NOP8 ".byte 0x0f,0x1f,0x84,0x00,0,0,0,0\n"
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#if defined(CONFIG_MK7)
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#define ASM_NOP1 K7_NOP1
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#define ASM_NOP2 K7_NOP2
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#define ASM_NOP3 K7_NOP3
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#define ASM_NOP4 K7_NOP4
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#define ASM_NOP5 K7_NOP5
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#define ASM_NOP6 K7_NOP6
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#define ASM_NOP7 K7_NOP7
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#define ASM_NOP8 K7_NOP8
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#elif defined(CONFIG_X86_P6_NOP)
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#define ASM_NOP1 P6_NOP1
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#define ASM_NOP2 P6_NOP2
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#define ASM_NOP3 P6_NOP3
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#define ASM_NOP4 P6_NOP4
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#define ASM_NOP5 P6_NOP5
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#define ASM_NOP6 P6_NOP6
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#define ASM_NOP7 P6_NOP7
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#define ASM_NOP8 P6_NOP8
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#elif defined(CONFIG_X86_64)
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#define ASM_NOP1 K8_NOP1
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#define ASM_NOP2 K8_NOP2
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#define ASM_NOP3 K8_NOP3
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#define ASM_NOP4 K8_NOP4
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#define ASM_NOP5 K8_NOP5
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#define ASM_NOP6 K8_NOP6
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#define ASM_NOP7 K8_NOP7
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#define ASM_NOP8 K8_NOP8
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#else
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#define ASM_NOP1 GENERIC_NOP1
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#define ASM_NOP2 GENERIC_NOP2
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#define ASM_NOP3 GENERIC_NOP3
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#define ASM_NOP4 GENERIC_NOP4
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#define ASM_NOP5 GENERIC_NOP5
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#define ASM_NOP6 GENERIC_NOP6
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#define ASM_NOP7 GENERIC_NOP7
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#define ASM_NOP8 GENERIC_NOP8
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#endif
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#define ASM_NOP_MAX 8
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#endif /* _ASM_X86_NOPS_H */
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