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3054a55c5d
Add a driver to control the clock divider found in the sample clock generator of the axg audio clock controller. The sclk divider accumulates specific features which make the generic divider unsuitable to control it: - zero based divider (div = val + 1), but zero value gates the clock, so minimum divider value is 2. - lrclk variant may adjust the duty cycle depending the divider value and the 'hi' value. Acked-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
29 lines
560 B
C
29 lines
560 B
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2018 BayLibre, SAS.
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* Author: Jerome Brunet <jbrunet@baylibre.com>
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*/
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#ifndef __MESON_CLKC_AUDIO_H
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#define __MESON_CLKC_AUDIO_H
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#include "clkc.h"
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struct meson_clk_triphase_data {
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struct parm ph0;
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struct parm ph1;
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struct parm ph2;
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};
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struct meson_sclk_div_data {
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struct parm div;
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struct parm hi;
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unsigned int cached_div;
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struct clk_duty cached_duty;
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};
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extern const struct clk_ops meson_clk_triphase_ops;
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extern const struct clk_ops meson_sclk_div_ops;
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#endif /* __MESON_CLKC_AUDIO_H */
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