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https://github.com/edk2-porting/linux-next.git
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b0d5217cfb
Add support for gpiolib calls. This is based on the gpiolib implementation from plat-s3c64xx tree. Add support for external interrupts for GPIO H banks. Add support for GPIO interrupts for all banks. Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Ben Dooks <ben-linux@fluff.org>
282 lines
5.9 KiB
C
282 lines
5.9 KiB
C
/*
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* linux/arch/arm/plat-s5pc1xx/irq-eint.c
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*
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* Copyright 2009 Samsung Electronics Co.
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* Byungho Min <bhmin@samsung.com>
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* Kyungin Park <kyungmin.park@samsung.com>
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*
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* Based on plat-s3c64xx/irq-eint.c
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*
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* S5PC1XX - Interrupt handling for IRQ_EINT(x)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/io.h>
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#include <linux/sysdev.h>
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#include <linux/pm.h>
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#include <linux/gpio.h>
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#include <asm/hardware/vic.h>
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#include <mach/map.h>
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#include <plat/gpio-cfg.h>
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#include <plat/gpio-ext.h>
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#include <plat/pm.h>
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#include <plat/regs-gpio.h>
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#include <plat/regs-irqtype.h>
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/*
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* bank is a group of external interrupt
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* bank0 means EINT0 ... EINT7
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* bank1 means EINT8 ... EINT15
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* bank2 means EINT16 ... EINT23
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* bank3 means EINT24 ... EINT31
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*/
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static inline int s3c_get_eint(unsigned int irq)
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{
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int real;
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if (irq < IRQ_EINT16_31)
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real = (irq - IRQ_EINT0);
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else
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real = (irq - S3C_IRQ_EINT_BASE) + IRQ_EINT16_31 - IRQ_EINT0;
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return real;
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}
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static inline int s3c_get_bank(unsigned int irq)
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{
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return s3c_get_eint(irq) >> 3;
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}
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static inline int s3c_eint_to_bit(unsigned int irq)
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{
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int real, bit;
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real = s3c_get_eint(irq);
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bit = 1 << (real & (8 - 1));
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return bit;
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}
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static inline void s3c_irq_eint_mask(unsigned int irq)
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{
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u32 mask;
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u32 bank = s3c_get_bank(irq);
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mask = __raw_readl(S5PC1XX_WKUP_INT_MASK(bank));
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mask |= s3c_eint_to_bit(irq);
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__raw_writel(mask, S5PC1XX_WKUP_INT_MASK(bank));
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}
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static void s3c_irq_eint_unmask(unsigned int irq)
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{
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u32 mask;
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u32 bank = s3c_get_bank(irq);
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mask = __raw_readl(S5PC1XX_WKUP_INT_MASK(bank));
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mask &= ~(s3c_eint_to_bit(irq));
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__raw_writel(mask, S5PC1XX_WKUP_INT_MASK(bank));
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}
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static inline void s3c_irq_eint_ack(unsigned int irq)
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{
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u32 bank = s3c_get_bank(irq);
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__raw_writel(s3c_eint_to_bit(irq), S5PC1XX_WKUP_INT_PEND(bank));
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}
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static void s3c_irq_eint_maskack(unsigned int irq)
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{
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/* compiler should in-line these */
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s3c_irq_eint_mask(irq);
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s3c_irq_eint_ack(irq);
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}
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static int s3c_irq_eint_set_type(unsigned int irq, unsigned int type)
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{
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u32 bank = s3c_get_bank(irq);
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int real = s3c_get_eint(irq);
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int gpio, shift, sfn;
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u32 ctrl, con = 0;
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switch (type) {
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case IRQ_TYPE_NONE:
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printk(KERN_WARNING "No edge setting!\n");
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break;
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case IRQ_TYPE_EDGE_RISING:
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con = S5PC1XX_WKUP_INT_RISEEDGE;
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break;
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case IRQ_TYPE_EDGE_FALLING:
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con = S5PC1XX_WKUP_INT_FALLEDGE;
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break;
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case IRQ_TYPE_EDGE_BOTH:
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con = S5PC1XX_WKUP_INT_BOTHEDGE;
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break;
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case IRQ_TYPE_LEVEL_LOW:
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con = S5PC1XX_WKUP_INT_LOWLEV;
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break;
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case IRQ_TYPE_LEVEL_HIGH:
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con = S5PC1XX_WKUP_INT_HILEV;
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break;
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default:
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printk(KERN_ERR "No such irq type %d", type);
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return -EINVAL;
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}
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gpio = real & (8 - 1);
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shift = gpio << 2;
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ctrl = __raw_readl(S5PC1XX_WKUP_INT_CON(bank));
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ctrl &= ~(0x7 << shift);
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ctrl |= con << shift;
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__raw_writel(ctrl, S5PC1XX_WKUP_INT_CON(bank));
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switch (real) {
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case 0 ... 7:
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gpio = S5PC100_GPH0(gpio);
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break;
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case 8 ... 15:
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gpio = S5PC100_GPH1(gpio);
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break;
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case 16 ... 23:
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gpio = S5PC100_GPH2(gpio);
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break;
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case 24 ... 31:
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gpio = S5PC100_GPH3(gpio);
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break;
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default:
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return -EINVAL;
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}
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sfn = S3C_GPIO_SFN(0x2);
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s3c_gpio_cfgpin(gpio, sfn);
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return 0;
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}
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static struct irq_chip s3c_irq_eint = {
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.name = "EINT",
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.mask = s3c_irq_eint_mask,
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.unmask = s3c_irq_eint_unmask,
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.mask_ack = s3c_irq_eint_maskack,
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.ack = s3c_irq_eint_ack,
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.set_type = s3c_irq_eint_set_type,
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.set_wake = s3c_irqext_wake,
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};
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/* s3c_irq_demux_eint
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*
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* This function demuxes the IRQ from external interrupts,
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* from IRQ_EINT(16) to IRQ_EINT(31). It is designed to be inlined into
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* the specific handlers s3c_irq_demux_eintX_Y.
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*/
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static inline void s3c_irq_demux_eint(unsigned int start, unsigned int end)
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{
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u32 status = __raw_readl(S5PC1XX_WKUP_INT_PEND((start >> 3)));
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u32 mask = __raw_readl(S5PC1XX_WKUP_INT_MASK((start >> 3)));
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unsigned int irq;
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status &= ~mask;
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status &= (1 << (end - start + 1)) - 1;
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for (irq = IRQ_EINT(start); irq <= IRQ_EINT(end); irq++) {
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if (status & 1)
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generic_handle_irq(irq);
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status >>= 1;
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}
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}
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static void s3c_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
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{
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s3c_irq_demux_eint(16, 23);
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s3c_irq_demux_eint(24, 31);
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}
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/*
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* Handle EINT0 ... EINT15 at VIC directly
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*/
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static void s3c_irq_vic_eint_mask(unsigned int irq)
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{
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void __iomem *base = get_irq_chip_data(irq);
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unsigned int real;
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s3c_irq_eint_mask(irq);
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real = s3c_get_eint(irq);
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writel(1 << real, base + VIC_INT_ENABLE_CLEAR);
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}
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static void s3c_irq_vic_eint_unmask(unsigned int irq)
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{
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void __iomem *base = get_irq_chip_data(irq);
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unsigned int real;
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s3c_irq_eint_unmask(irq);
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real = s3c_get_eint(irq);
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writel(1 << real, base + VIC_INT_ENABLE);
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}
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static inline void s3c_irq_vic_eint_ack(unsigned int irq)
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{
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u32 bit;
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u32 bank = s3c_get_bank(irq);
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bit = s3c_eint_to_bit(irq);
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__raw_writel(bit, S5PC1XX_WKUP_INT_PEND(bank));
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}
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static void s3c_irq_vic_eint_maskack(unsigned int irq)
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{
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/* compiler should in-line these */
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s3c_irq_vic_eint_mask(irq);
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s3c_irq_vic_eint_ack(irq);
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}
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static struct irq_chip s3c_irq_vic_eint = {
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.name = "EINT",
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.mask = s3c_irq_vic_eint_mask,
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.unmask = s3c_irq_vic_eint_unmask,
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.mask_ack = s3c_irq_vic_eint_maskack,
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.ack = s3c_irq_vic_eint_ack,
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.set_type = s3c_irq_eint_set_type,
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.set_wake = s3c_irqext_wake,
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};
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static int __init s5pc1xx_init_irq_eint(void)
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{
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int irq;
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for (irq = IRQ_EINT0; irq <= IRQ_EINT15; irq++) {
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set_irq_chip(irq, &s3c_irq_vic_eint);
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set_irq_handler(irq, handle_level_irq);
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set_irq_flags(irq, IRQF_VALID);
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}
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for (irq = IRQ_EINT(16); irq <= IRQ_EINT(31); irq++) {
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set_irq_chip(irq, &s3c_irq_eint);
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set_irq_handler(irq, handle_level_irq);
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set_irq_flags(irq, IRQF_VALID);
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}
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set_irq_chained_handler(IRQ_EINT16_31, s3c_irq_demux_eint16_31);
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return 0;
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}
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arch_initcall(s5pc1xx_init_irq_eint);
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