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cd24834130
Add PCI support for s390, (only 64 bit mode is supported by hardware): - PCI facility tests - PCI instructions: pcilg, pcistg, pcistb, stpcifc, mpcifc, rpcit - map readb/w/l/q and writeb/w/l/q to pcilg and pcistg instructions - pci_iomap implementation - memcpy_fromio/toio - pci_root_ops using special pcilg/pcistg - device, bus and domain allocation Signed-off-by: Jan Glauber <jang@linux.vnet.ibm.com> Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
281 lines
6.7 KiB
C
281 lines
6.7 KiB
C
#ifndef _ASM_S390_PCI_INSN_H
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#define _ASM_S390_PCI_INSN_H
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#include <linux/delay.h>
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#define ZPCI_INSN_BUSY_DELAY 1 /* 1 millisecond */
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/* Load/Store status codes */
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#define ZPCI_PCI_ST_FUNC_NOT_ENABLED 4
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#define ZPCI_PCI_ST_FUNC_IN_ERR 8
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#define ZPCI_PCI_ST_BLOCKED 12
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#define ZPCI_PCI_ST_INSUF_RES 16
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#define ZPCI_PCI_ST_INVAL_AS 20
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#define ZPCI_PCI_ST_FUNC_ALREADY_ENABLED 24
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#define ZPCI_PCI_ST_DMA_AS_NOT_ENABLED 28
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#define ZPCI_PCI_ST_2ND_OP_IN_INV_AS 36
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#define ZPCI_PCI_ST_FUNC_NOT_AVAIL 40
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#define ZPCI_PCI_ST_ALREADY_IN_RQ_STATE 44
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/* Load/Store return codes */
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#define ZPCI_PCI_LS_OK 0
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#define ZPCI_PCI_LS_ERR 1
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#define ZPCI_PCI_LS_BUSY 2
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#define ZPCI_PCI_LS_INVAL_HANDLE 3
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/* Load/Store address space identifiers */
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#define ZPCI_PCIAS_MEMIO_0 0
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#define ZPCI_PCIAS_MEMIO_1 1
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#define ZPCI_PCIAS_MEMIO_2 2
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#define ZPCI_PCIAS_MEMIO_3 3
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#define ZPCI_PCIAS_MEMIO_4 4
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#define ZPCI_PCIAS_MEMIO_5 5
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#define ZPCI_PCIAS_CFGSPC 15
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/* Modify PCI Function Controls */
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#define ZPCI_MOD_FC_REG_INT 2
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#define ZPCI_MOD_FC_DEREG_INT 3
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#define ZPCI_MOD_FC_REG_IOAT 4
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#define ZPCI_MOD_FC_DEREG_IOAT 5
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#define ZPCI_MOD_FC_REREG_IOAT 6
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#define ZPCI_MOD_FC_RESET_ERROR 7
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#define ZPCI_MOD_FC_RESET_BLOCK 9
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#define ZPCI_MOD_FC_SET_MEASURE 10
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/* FIB function controls */
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#define ZPCI_FIB_FC_ENABLED 0x80
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#define ZPCI_FIB_FC_ERROR 0x40
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#define ZPCI_FIB_FC_LS_BLOCKED 0x20
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#define ZPCI_FIB_FC_DMAAS_REG 0x10
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/* FIB function controls */
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#define ZPCI_FIB_FC_ENABLED 0x80
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#define ZPCI_FIB_FC_ERROR 0x40
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#define ZPCI_FIB_FC_LS_BLOCKED 0x20
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#define ZPCI_FIB_FC_DMAAS_REG 0x10
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/* Function Information Block */
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struct zpci_fib {
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u32 fmt : 8; /* format */
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u32 : 24;
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u32 reserved1;
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u8 fc; /* function controls */
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u8 reserved2;
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u16 reserved3;
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u32 reserved4;
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u64 pba; /* PCI base address */
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u64 pal; /* PCI address limit */
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u64 iota; /* I/O Translation Anchor */
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u32 : 1;
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u32 isc : 3; /* Interrupt subclass */
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u32 noi : 12; /* Number of interrupts */
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u32 : 2;
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u32 aibvo : 6; /* Adapter interrupt bit vector offset */
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u32 sum : 1; /* Adapter int summary bit enabled */
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u32 : 1;
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u32 aisbo : 6; /* Adapter int summary bit offset */
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u32 reserved5;
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u64 aibv; /* Adapter int bit vector address */
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u64 aisb; /* Adapter int summary bit address */
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u64 fmb_addr; /* Function measurement block address and key */
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u64 reserved6;
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u64 reserved7;
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} __packed;
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/* Modify PCI Function Controls */
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static inline u8 __mpcifc(u64 req, struct zpci_fib *fib, u8 *status)
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{
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u8 cc;
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asm volatile (
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" .insn rxy,0xe300000000d0,%[req],%[fib]\n"
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" ipm %[cc]\n"
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" srl %[cc],28\n"
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: [cc] "=d" (cc), [req] "+d" (req), [fib] "+Q" (*fib)
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: : "cc");
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*status = req >> 24 & 0xff;
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return cc;
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}
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static inline int mpcifc_instr(u64 req, struct zpci_fib *fib)
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{
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u8 cc, status;
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do {
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cc = __mpcifc(req, fib, &status);
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if (cc == 2)
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msleep(ZPCI_INSN_BUSY_DELAY);
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} while (cc == 2);
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if (cc)
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printk_once(KERN_ERR "%s: error cc: %d status: %d\n",
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__func__, cc, status);
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return (cc) ? -EIO : 0;
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}
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/* Refresh PCI Translations */
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static inline u8 __rpcit(u64 fn, u64 addr, u64 range, u8 *status)
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{
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register u64 __addr asm("2") = addr;
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register u64 __range asm("3") = range;
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u8 cc;
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asm volatile (
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" .insn rre,0xb9d30000,%[fn],%[addr]\n"
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" ipm %[cc]\n"
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" srl %[cc],28\n"
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: [cc] "=d" (cc), [fn] "+d" (fn)
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: [addr] "d" (__addr), "d" (__range)
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: "cc");
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*status = fn >> 24 & 0xff;
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return cc;
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}
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static inline int rpcit_instr(u64 fn, u64 addr, u64 range)
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{
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u8 cc, status;
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do {
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cc = __rpcit(fn, addr, range, &status);
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if (cc == 2)
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msleep(ZPCI_INSN_BUSY_DELAY);
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} while (cc == 2);
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if (cc)
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printk_once(KERN_ERR "%s: error cc: %d status: %d dma_addr: %Lx size: %Lx\n",
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__func__, cc, status, addr, range);
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return (cc) ? -EIO : 0;
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}
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/* Store PCI function controls */
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static inline u8 __stpcifc(u32 handle, u8 space, struct zpci_fib *fib, u8 *status)
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{
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u64 fn = (u64) handle << 32 | space << 16;
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u8 cc;
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asm volatile (
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" .insn rxy,0xe300000000d4,%[fn],%[fib]\n"
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" ipm %[cc]\n"
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" srl %[cc],28\n"
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: [cc] "=d" (cc), [fn] "+d" (fn), [fib] "=m" (*fib)
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: : "cc");
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*status = fn >> 24 & 0xff;
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return cc;
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}
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/* Set Interruption Controls */
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static inline void sic_instr(u16 ctl, char *unused, u8 isc)
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{
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asm volatile (
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" .insn rsy,0xeb00000000d1,%[ctl],%[isc],%[u]\n"
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: : [ctl] "d" (ctl), [isc] "d" (isc << 27), [u] "Q" (*unused));
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}
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/* PCI Load */
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static inline u8 __pcilg(u64 *data, u64 req, u64 offset, u8 *status)
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{
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register u64 __req asm("2") = req;
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register u64 __offset asm("3") = offset;
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u64 __data;
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u8 cc;
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asm volatile (
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" .insn rre,0xb9d20000,%[data],%[req]\n"
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" ipm %[cc]\n"
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" srl %[cc],28\n"
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: [cc] "=d" (cc), [data] "=d" (__data), [req] "+d" (__req)
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: "d" (__offset)
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: "cc");
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*status = __req >> 24 & 0xff;
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*data = __data;
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return cc;
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}
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static inline int pcilg_instr(u64 *data, u64 req, u64 offset)
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{
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u8 cc, status;
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do {
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cc = __pcilg(data, req, offset, &status);
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if (cc == 2)
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msleep(ZPCI_INSN_BUSY_DELAY);
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} while (cc == 2);
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if (cc) {
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printk_once(KERN_ERR "%s: error cc: %d status: %d req: %Lx offset: %Lx\n",
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__func__, cc, status, req, offset);
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/* TODO: on IO errors set data to 0xff...
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* here or in users of pcilg (le conversion)?
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*/
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}
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return (cc) ? -EIO : 0;
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}
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/* PCI Store */
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static inline u8 __pcistg(u64 data, u64 req, u64 offset, u8 *status)
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{
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register u64 __req asm("2") = req;
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register u64 __offset asm("3") = offset;
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u8 cc;
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asm volatile (
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" .insn rre,0xb9d00000,%[data],%[req]\n"
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" ipm %[cc]\n"
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" srl %[cc],28\n"
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: [cc] "=d" (cc), [req] "+d" (__req)
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: "d" (__offset), [data] "d" (data)
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: "cc");
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*status = __req >> 24 & 0xff;
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return cc;
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}
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static inline int pcistg_instr(u64 data, u64 req, u64 offset)
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{
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u8 cc, status;
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do {
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cc = __pcistg(data, req, offset, &status);
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if (cc == 2)
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msleep(ZPCI_INSN_BUSY_DELAY);
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} while (cc == 2);
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if (cc)
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printk_once(KERN_ERR "%s: error cc: %d status: %d req: %Lx offset: %Lx\n",
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__func__, cc, status, req, offset);
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return (cc) ? -EIO : 0;
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}
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/* PCI Store Block */
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static inline u8 __pcistb(const u64 *data, u64 req, u64 offset, u8 *status)
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{
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u8 cc;
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asm volatile (
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" .insn rsy,0xeb00000000d0,%[req],%[offset],%[data]\n"
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" ipm %[cc]\n"
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" srl %[cc],28\n"
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: [cc] "=d" (cc), [req] "+d" (req)
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: [offset] "d" (offset), [data] "Q" (*data)
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: "cc");
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*status = req >> 24 & 0xff;
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return cc;
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}
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static inline int pcistb_instr(const u64 *data, u64 req, u64 offset)
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{
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u8 cc, status;
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do {
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cc = __pcistb(data, req, offset, &status);
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if (cc == 2)
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msleep(ZPCI_INSN_BUSY_DELAY);
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} while (cc == 2);
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if (cc)
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printk_once(KERN_ERR "%s: error cc: %d status: %d req: %Lx offset: %Lx\n",
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__func__, cc, status, req, offset);
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return (cc) ? -EIO : 0;
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}
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#endif
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