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830145796a
The arch/arm/mach-exynos4 directory (CONFIG_ARCH_EXYNOS4) has made for plaforms based on EXYNOS4 SoCs. But since upcoming Samsung's SoCs such as EXYNOS5 (ARM Cortex A15) can reuse most codes in current mach-exynos4, one mach-exynos directory will be used for them. This patch changes to CONFIG_ARCH_EXYNOS (arch/arm/mach-exynos) but keeps original CONFIG_ARCH_EXYNOS4 in mach-exynos/Kconfig to avoid changing in driver side. Cc: Arnd Bergmann <arnd@arndb.de> Cc: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
370 lines
7.6 KiB
C
370 lines
7.6 KiB
C
/* linux/arch/arm/mach-exynos4/dev-audio.c
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*
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* Copyright (c) 2011 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* Copyright (c) 2010 Samsung Electronics Co. Ltd
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* Jaswinder Singh <jassi.brar@samsung.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/platform_device.h>
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#include <linux/dma-mapping.h>
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#include <linux/gpio.h>
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#include <plat/gpio-cfg.h>
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#include <plat/audio.h>
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#include <mach/map.h>
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#include <mach/dma.h>
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#include <mach/irqs.h>
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#include <mach/regs-audss.h>
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static const char *rclksrc[] = {
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[0] = "busclk",
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[1] = "i2sclk",
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};
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static int exynos4_cfg_i2s(struct platform_device *pdev)
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{
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/* configure GPIO for i2s port */
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switch (pdev->id) {
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case 0:
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s3c_gpio_cfgpin_range(EXYNOS4_GPZ(0), 7, S3C_GPIO_SFN(2));
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break;
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case 1:
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s3c_gpio_cfgpin_range(EXYNOS4_GPC0(0), 5, S3C_GPIO_SFN(2));
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break;
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case 2:
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s3c_gpio_cfgpin_range(EXYNOS4_GPC1(0), 5, S3C_GPIO_SFN(4));
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break;
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default:
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printk(KERN_ERR "Invalid Device %d\n", pdev->id);
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return -EINVAL;
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}
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return 0;
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}
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static struct s3c_audio_pdata i2sv5_pdata = {
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.cfg_gpio = exynos4_cfg_i2s,
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.type = {
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.i2s = {
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.quirks = QUIRK_PRI_6CHAN | QUIRK_SEC_DAI
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| QUIRK_NEED_RSTCLR,
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.src_clk = rclksrc,
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.idma_addr = EXYNOS4_AUDSS_INT_MEM,
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},
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},
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};
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static struct resource exynos4_i2s0_resource[] = {
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[0] = {
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.start = EXYNOS4_PA_I2S0,
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.end = EXYNOS4_PA_I2S0 + 0x100 - 1,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = DMACH_I2S0_TX,
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.end = DMACH_I2S0_TX,
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.flags = IORESOURCE_DMA,
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},
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[2] = {
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.start = DMACH_I2S0_RX,
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.end = DMACH_I2S0_RX,
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.flags = IORESOURCE_DMA,
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},
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[3] = {
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.start = DMACH_I2S0S_TX,
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.end = DMACH_I2S0S_TX,
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.flags = IORESOURCE_DMA,
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},
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};
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struct platform_device exynos4_device_i2s0 = {
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.name = "samsung-i2s",
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.id = 0,
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.num_resources = ARRAY_SIZE(exynos4_i2s0_resource),
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.resource = exynos4_i2s0_resource,
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.dev = {
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.platform_data = &i2sv5_pdata,
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},
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};
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static const char *rclksrc_v3[] = {
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[0] = "sclk_i2s",
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[1] = "no_such_clock",
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};
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static struct s3c_audio_pdata i2sv3_pdata = {
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.cfg_gpio = exynos4_cfg_i2s,
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.type = {
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.i2s = {
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.quirks = QUIRK_NO_MUXPSR,
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.src_clk = rclksrc_v3,
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},
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},
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};
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static struct resource exynos4_i2s1_resource[] = {
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[0] = {
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.start = EXYNOS4_PA_I2S1,
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.end = EXYNOS4_PA_I2S1 + 0x100 - 1,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = DMACH_I2S1_TX,
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.end = DMACH_I2S1_TX,
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.flags = IORESOURCE_DMA,
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},
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[2] = {
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.start = DMACH_I2S1_RX,
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.end = DMACH_I2S1_RX,
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.flags = IORESOURCE_DMA,
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},
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};
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struct platform_device exynos4_device_i2s1 = {
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.name = "samsung-i2s",
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.id = 1,
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.num_resources = ARRAY_SIZE(exynos4_i2s1_resource),
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.resource = exynos4_i2s1_resource,
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.dev = {
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.platform_data = &i2sv3_pdata,
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},
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};
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static struct resource exynos4_i2s2_resource[] = {
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[0] = {
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.start = EXYNOS4_PA_I2S2,
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.end = EXYNOS4_PA_I2S2 + 0x100 - 1,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = DMACH_I2S2_TX,
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.end = DMACH_I2S2_TX,
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.flags = IORESOURCE_DMA,
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},
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[2] = {
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.start = DMACH_I2S2_RX,
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.end = DMACH_I2S2_RX,
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.flags = IORESOURCE_DMA,
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},
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};
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struct platform_device exynos4_device_i2s2 = {
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.name = "samsung-i2s",
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.id = 2,
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.num_resources = ARRAY_SIZE(exynos4_i2s2_resource),
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.resource = exynos4_i2s2_resource,
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.dev = {
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.platform_data = &i2sv3_pdata,
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},
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};
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/* PCM Controller platform_devices */
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static int exynos4_pcm_cfg_gpio(struct platform_device *pdev)
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{
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switch (pdev->id) {
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case 0:
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s3c_gpio_cfgpin_range(EXYNOS4_GPZ(0), 5, S3C_GPIO_SFN(3));
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break;
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case 1:
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s3c_gpio_cfgpin_range(EXYNOS4_GPC0(0), 5, S3C_GPIO_SFN(3));
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break;
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case 2:
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s3c_gpio_cfgpin_range(EXYNOS4_GPC1(0), 5, S3C_GPIO_SFN(3));
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break;
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default:
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printk(KERN_DEBUG "Invalid PCM Controller number!");
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return -EINVAL;
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}
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return 0;
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}
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static struct s3c_audio_pdata s3c_pcm_pdata = {
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.cfg_gpio = exynos4_pcm_cfg_gpio,
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};
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static struct resource exynos4_pcm0_resource[] = {
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[0] = {
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.start = EXYNOS4_PA_PCM0,
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.end = EXYNOS4_PA_PCM0 + 0x100 - 1,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = DMACH_PCM0_TX,
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.end = DMACH_PCM0_TX,
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.flags = IORESOURCE_DMA,
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},
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[2] = {
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.start = DMACH_PCM0_RX,
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.end = DMACH_PCM0_RX,
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.flags = IORESOURCE_DMA,
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},
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};
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struct platform_device exynos4_device_pcm0 = {
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.name = "samsung-pcm",
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.id = 0,
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.num_resources = ARRAY_SIZE(exynos4_pcm0_resource),
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.resource = exynos4_pcm0_resource,
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.dev = {
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.platform_data = &s3c_pcm_pdata,
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},
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};
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static struct resource exynos4_pcm1_resource[] = {
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[0] = {
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.start = EXYNOS4_PA_PCM1,
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.end = EXYNOS4_PA_PCM1 + 0x100 - 1,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = DMACH_PCM1_TX,
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.end = DMACH_PCM1_TX,
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.flags = IORESOURCE_DMA,
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},
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[2] = {
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.start = DMACH_PCM1_RX,
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.end = DMACH_PCM1_RX,
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.flags = IORESOURCE_DMA,
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},
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};
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struct platform_device exynos4_device_pcm1 = {
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.name = "samsung-pcm",
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.id = 1,
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.num_resources = ARRAY_SIZE(exynos4_pcm1_resource),
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.resource = exynos4_pcm1_resource,
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.dev = {
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.platform_data = &s3c_pcm_pdata,
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},
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};
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static struct resource exynos4_pcm2_resource[] = {
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[0] = {
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.start = EXYNOS4_PA_PCM2,
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.end = EXYNOS4_PA_PCM2 + 0x100 - 1,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = DMACH_PCM2_TX,
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.end = DMACH_PCM2_TX,
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.flags = IORESOURCE_DMA,
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},
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[2] = {
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.start = DMACH_PCM2_RX,
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.end = DMACH_PCM2_RX,
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.flags = IORESOURCE_DMA,
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},
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};
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struct platform_device exynos4_device_pcm2 = {
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.name = "samsung-pcm",
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.id = 2,
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.num_resources = ARRAY_SIZE(exynos4_pcm2_resource),
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.resource = exynos4_pcm2_resource,
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.dev = {
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.platform_data = &s3c_pcm_pdata,
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},
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};
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/* AC97 Controller platform devices */
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static int exynos4_ac97_cfg_gpio(struct platform_device *pdev)
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{
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return s3c_gpio_cfgpin_range(EXYNOS4_GPC0(0), 5, S3C_GPIO_SFN(4));
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}
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static struct resource exynos4_ac97_resource[] = {
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[0] = {
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.start = EXYNOS4_PA_AC97,
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.end = EXYNOS4_PA_AC97 + 0x100 - 1,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = DMACH_AC97_PCMOUT,
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.end = DMACH_AC97_PCMOUT,
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.flags = IORESOURCE_DMA,
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},
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[2] = {
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.start = DMACH_AC97_PCMIN,
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.end = DMACH_AC97_PCMIN,
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.flags = IORESOURCE_DMA,
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},
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[3] = {
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.start = DMACH_AC97_MICIN,
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.end = DMACH_AC97_MICIN,
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.flags = IORESOURCE_DMA,
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},
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[4] = {
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.start = IRQ_AC97,
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.end = IRQ_AC97,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct s3c_audio_pdata s3c_ac97_pdata = {
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.cfg_gpio = exynos4_ac97_cfg_gpio,
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};
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static u64 exynos4_ac97_dmamask = DMA_BIT_MASK(32);
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struct platform_device exynos4_device_ac97 = {
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.name = "samsung-ac97",
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.id = -1,
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.num_resources = ARRAY_SIZE(exynos4_ac97_resource),
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.resource = exynos4_ac97_resource,
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.dev = {
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.platform_data = &s3c_ac97_pdata,
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.dma_mask = &exynos4_ac97_dmamask,
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.coherent_dma_mask = DMA_BIT_MASK(32),
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},
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};
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/* S/PDIF Controller platform_device */
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static int exynos4_spdif_cfg_gpio(struct platform_device *pdev)
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{
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s3c_gpio_cfgpin_range(EXYNOS4_GPC1(0), 2, S3C_GPIO_SFN(4));
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return 0;
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}
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static struct resource exynos4_spdif_resource[] = {
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[0] = {
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.start = EXYNOS4_PA_SPDIF,
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.end = EXYNOS4_PA_SPDIF + 0x100 - 1,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = DMACH_SPDIF,
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.end = DMACH_SPDIF,
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.flags = IORESOURCE_DMA,
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},
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};
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static struct s3c_audio_pdata samsung_spdif_pdata = {
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.cfg_gpio = exynos4_spdif_cfg_gpio,
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};
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static u64 exynos4_spdif_dmamask = DMA_BIT_MASK(32);
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struct platform_device exynos4_device_spdif = {
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.name = "samsung-spdif",
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.id = -1,
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.num_resources = ARRAY_SIZE(exynos4_spdif_resource),
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.resource = exynos4_spdif_resource,
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.dev = {
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.platform_data = &samsung_spdif_pdata,
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.dma_mask = &exynos4_spdif_dmamask,
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.coherent_dma_mask = DMA_BIT_MASK(32),
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},
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};
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