mirror of
https://github.com/edk2-porting/linux-next.git
synced 2024-12-25 21:54:06 +08:00
faff3d8e85
* clk-renesas: (36 commits) clk: renesas: r7s9210: Add SPI clocks clk: renesas: r7s9210: Move table update to separate function clk: renesas: r7s9210: Convert some clocks to early clk: renesas: cpg-mssr: Add early clock support clk: renesas: r8a77970: Add TPU clock clk: renesas: r8a77990: Fix incorrect PLL0 divider in comment dt-bindings: clock: renesas: cpg-mssr: Document r8a774c0 clk: renesas: cpg-mssr: Add r8a774c0 support clk: renesas: Add r8a774c0 CPG Core Clock Definitions clk: renesas: r8a7743: Add r8a7744 support clk: renesas: Add r8a7744 CPG Core Clock Definitions dt-bindings: clock: renesas: cpg-mssr: Document r8a7744 binding dt-bindings: clock: renesas: Convert to SPDX identifiers clk: renesas: cpg-mssr: Add R7S9210 support clk: renesas: r8a77970: Add TMU clocks clk: renesas: r8a77970: Add CMT clocks clk: renesas: r9a06g032: Fix UART34567 clock rate clk: renesas: r8a77970: Add SD0H/SD0 clocks for SDHI clk: renesas: r8a77980: Add CMT clocks clk: renesas: r8a77990: Add missing I2C7 clock ...
70 lines
2.0 KiB
C
70 lines
2.0 KiB
C
/* SPDX-License-Identifier: GPL-2.0
|
|
*
|
|
* R-Car Gen3 Clock Pulse Generator
|
|
*
|
|
* Copyright (C) 2015-2018 Glider bvba
|
|
*
|
|
*/
|
|
|
|
#ifndef __CLK_RENESAS_RCAR_GEN3_CPG_H__
|
|
#define __CLK_RENESAS_RCAR_GEN3_CPG_H__
|
|
|
|
enum rcar_gen3_clk_types {
|
|
CLK_TYPE_GEN3_MAIN = CLK_TYPE_CUSTOM,
|
|
CLK_TYPE_GEN3_PLL0,
|
|
CLK_TYPE_GEN3_PLL1,
|
|
CLK_TYPE_GEN3_PLL2,
|
|
CLK_TYPE_GEN3_PLL3,
|
|
CLK_TYPE_GEN3_PLL4,
|
|
CLK_TYPE_GEN3_SD,
|
|
CLK_TYPE_GEN3_R,
|
|
CLK_TYPE_GEN3_MDSEL, /* Select parent/divider using mode pin */
|
|
CLK_TYPE_GEN3_Z,
|
|
CLK_TYPE_GEN3_Z2,
|
|
CLK_TYPE_GEN3_OSC, /* OSC EXTAL predivider and fixed divider */
|
|
CLK_TYPE_GEN3_RCKSEL, /* Select parent/divider using RCKCR.CKSEL */
|
|
|
|
/* SoC specific definitions start here */
|
|
CLK_TYPE_GEN3_SOC_BASE,
|
|
};
|
|
|
|
#define DEF_GEN3_SD(_name, _id, _parent, _offset) \
|
|
DEF_BASE(_name, _id, CLK_TYPE_GEN3_SD, _parent, .offset = _offset)
|
|
|
|
#define DEF_GEN3_MDSEL(_name, _id, _md, _parent0, _div0, _parent1, _div1) \
|
|
DEF_BASE(_name, _id, CLK_TYPE_GEN3_MDSEL, \
|
|
(_parent0) << 16 | (_parent1), \
|
|
.div = (_div0) << 16 | (_div1), .offset = _md)
|
|
|
|
#define DEF_GEN3_PE(_name, _id, _parent_sscg, _div_sscg, _parent_clean, \
|
|
_div_clean) \
|
|
DEF_GEN3_MDSEL(_name, _id, 12, _parent_sscg, _div_sscg, \
|
|
_parent_clean, _div_clean)
|
|
|
|
#define DEF_GEN3_OSC(_name, _id, _parent, _div) \
|
|
DEF_BASE(_name, _id, CLK_TYPE_GEN3_OSC, _parent, .div = _div)
|
|
|
|
#define DEF_GEN3_RCKSEL(_name, _id, _parent0, _div0, _parent1, _div1) \
|
|
DEF_BASE(_name, _id, CLK_TYPE_GEN3_RCKSEL, \
|
|
(_parent0) << 16 | (_parent1), .div = (_div0) << 16 | (_div1))
|
|
|
|
struct rcar_gen3_cpg_pll_config {
|
|
u8 extal_div;
|
|
u8 pll1_mult;
|
|
u8 pll1_div;
|
|
u8 pll3_mult;
|
|
u8 pll3_div;
|
|
u8 osc_prediv;
|
|
};
|
|
|
|
#define CPG_RCKCR 0x240
|
|
|
|
struct clk *rcar_gen3_cpg_clk_register(struct device *dev,
|
|
const struct cpg_core_clk *core, const struct cpg_mssr_info *info,
|
|
struct clk **clks, void __iomem *base,
|
|
struct raw_notifier_head *notifiers);
|
|
int rcar_gen3_cpg_init(const struct rcar_gen3_cpg_pll_config *config,
|
|
unsigned int clk_extalr, u32 mode);
|
|
|
|
#endif
|