mirror of
https://github.com/edk2-porting/linux-next.git
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275 lines
5.7 KiB
C
275 lines
5.7 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2000-2004 Silicon Graphics, Inc. All rights reserved.
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*/
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#ifndef _ASM_SN_IO_H
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#define _ASM_SN_IO_H
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#include <linux/compiler.h>
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#include <asm/intrinsics.h>
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extern void * sn_io_addr(unsigned long port) __attribute_const__; /* Forward definition */
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extern void __sn_mmiowb(void); /* Forward definition */
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extern int num_cnodes;
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#define __sn_mf_a() ia64_mfa()
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extern void sn_dma_flush(unsigned long);
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#define __sn_inb ___sn_inb
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#define __sn_inw ___sn_inw
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#define __sn_inl ___sn_inl
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#define __sn_outb ___sn_outb
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#define __sn_outw ___sn_outw
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#define __sn_outl ___sn_outl
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#define __sn_readb ___sn_readb
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#define __sn_readw ___sn_readw
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#define __sn_readl ___sn_readl
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#define __sn_readq ___sn_readq
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#define __sn_readb_relaxed ___sn_readb_relaxed
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#define __sn_readw_relaxed ___sn_readw_relaxed
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#define __sn_readl_relaxed ___sn_readl_relaxed
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#define __sn_readq_relaxed ___sn_readq_relaxed
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/*
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* Convenience macros for setting/clearing bits using the above accessors
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*/
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#define __sn_setq_relaxed(addr, val) \
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writeq((__sn_readq_relaxed(addr) | (val)), (addr))
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#define __sn_clrq_relaxed(addr, val) \
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writeq((__sn_readq_relaxed(addr) & ~(val)), (addr))
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/*
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* The following routines are SN Platform specific, called when
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* a reference is made to inX/outX set macros. SN Platform
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* inX set of macros ensures that Posted DMA writes on the
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* Bridge is flushed.
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*
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* The routines should be self explainatory.
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*/
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static inline unsigned int
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___sn_inb (unsigned long port)
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{
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volatile unsigned char *addr;
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unsigned char ret = -1;
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if ((addr = sn_io_addr(port))) {
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ret = *addr;
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__sn_mf_a();
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sn_dma_flush((unsigned long)addr);
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}
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return ret;
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}
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static inline unsigned int
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___sn_inw (unsigned long port)
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{
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volatile unsigned short *addr;
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unsigned short ret = -1;
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if ((addr = sn_io_addr(port))) {
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ret = *addr;
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__sn_mf_a();
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sn_dma_flush((unsigned long)addr);
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}
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return ret;
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}
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static inline unsigned int
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___sn_inl (unsigned long port)
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{
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volatile unsigned int *addr;
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unsigned int ret = -1;
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if ((addr = sn_io_addr(port))) {
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ret = *addr;
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__sn_mf_a();
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sn_dma_flush((unsigned long)addr);
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}
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return ret;
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}
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static inline void
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___sn_outb (unsigned char val, unsigned long port)
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{
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volatile unsigned char *addr;
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if ((addr = sn_io_addr(port))) {
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*addr = val;
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__sn_mmiowb();
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}
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}
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static inline void
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___sn_outw (unsigned short val, unsigned long port)
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{
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volatile unsigned short *addr;
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if ((addr = sn_io_addr(port))) {
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*addr = val;
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__sn_mmiowb();
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}
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}
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static inline void
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___sn_outl (unsigned int val, unsigned long port)
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{
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volatile unsigned int *addr;
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if ((addr = sn_io_addr(port))) {
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*addr = val;
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__sn_mmiowb();
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}
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}
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/*
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* The following routines are SN Platform specific, called when
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* a reference is made to readX/writeX set macros. SN Platform
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* readX set of macros ensures that Posted DMA writes on the
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* Bridge is flushed.
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*
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* The routines should be self explainatory.
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*/
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static inline unsigned char
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___sn_readb (const volatile void __iomem *addr)
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{
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unsigned char val;
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val = *(volatile unsigned char __force *)addr;
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__sn_mf_a();
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sn_dma_flush((unsigned long)addr);
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return val;
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}
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static inline unsigned short
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___sn_readw (const volatile void __iomem *addr)
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{
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unsigned short val;
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val = *(volatile unsigned short __force *)addr;
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__sn_mf_a();
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sn_dma_flush((unsigned long)addr);
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return val;
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}
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static inline unsigned int
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___sn_readl (const volatile void __iomem *addr)
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{
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unsigned int val;
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val = *(volatile unsigned int __force *)addr;
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__sn_mf_a();
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sn_dma_flush((unsigned long)addr);
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return val;
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}
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static inline unsigned long
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___sn_readq (const volatile void __iomem *addr)
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{
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unsigned long val;
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val = *(volatile unsigned long __force *)addr;
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__sn_mf_a();
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sn_dma_flush((unsigned long)addr);
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return val;
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}
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/*
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* For generic and SN2 kernels, we have a set of fast access
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* PIO macros. These macros are provided on SN Platform
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* because the normal inX and readX macros perform an
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* additional task of flushing Post DMA request on the Bridge.
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*
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* These routines should be self explainatory.
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*/
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static inline unsigned int
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sn_inb_fast (unsigned long port)
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{
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volatile unsigned char *addr = (unsigned char *)port;
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unsigned char ret;
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ret = *addr;
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__sn_mf_a();
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return ret;
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}
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static inline unsigned int
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sn_inw_fast (unsigned long port)
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{
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volatile unsigned short *addr = (unsigned short *)port;
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unsigned short ret;
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ret = *addr;
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__sn_mf_a();
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return ret;
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}
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static inline unsigned int
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sn_inl_fast (unsigned long port)
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{
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volatile unsigned int *addr = (unsigned int *)port;
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unsigned int ret;
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ret = *addr;
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__sn_mf_a();
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return ret;
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}
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static inline unsigned char
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___sn_readb_relaxed (const volatile void __iomem *addr)
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{
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return *(volatile unsigned char __force *)addr;
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}
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static inline unsigned short
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___sn_readw_relaxed (const volatile void __iomem *addr)
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{
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return *(volatile unsigned short __force *)addr;
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}
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static inline unsigned int
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___sn_readl_relaxed (const volatile void __iomem *addr)
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{
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return *(volatile unsigned int __force *) addr;
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}
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static inline unsigned long
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___sn_readq_relaxed (const volatile void __iomem *addr)
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{
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return *(volatile unsigned long __force *) addr;
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}
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struct pci_dev;
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static inline int
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sn_pci_set_vchan(struct pci_dev *pci_dev, unsigned long *addr, int vchan)
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{
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if (vchan > 1) {
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return -1;
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}
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if (!(*addr >> 32)) /* Using a mask here would be cleaner */
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return 0; /* but this generates better code */
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if (vchan == 1) {
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/* Set Bit 57 */
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*addr |= (1UL << 57);
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} else {
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/* Clear Bit 57 */
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*addr &= ~(1UL << 57);
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}
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return 0;
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}
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#endif /* _ASM_SN_IO_H */
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