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54b4a8f578
Add support for the Arria10 SDRAM EDAC. Update the bindings document for the new match string. Signed-off-by: Thor Thayer <tthayer@opensource.altera.com> Cc: Arnd Bergmann <arnd@arndb.de> Cc: devicetree@vger.kernel.org Cc: dinguyen@opensource.altera.com Cc: galak@codeaurora.org Cc: grant.likely@linaro.org Cc: ijc+devicetree@hellion.org.uk Cc: linux-arm-kernel@lists.infradead.org Cc: linux-edac <linux-edac@vger.kernel.org> Cc: m.chehab@samsung.com Cc: mark.rutland@arm.com Cc: pawel.moll@arm.com Cc: robh+dt@kernel.org Cc: tthayer.linux@gmail.com Link: http://lkml.kernel.org/r/1433428128-7292-5-git-send-email-tthayer@opensource.altera.com Signed-off-by: Borislav Petkov <bp@suse.de>
16 lines
475 B
Plaintext
16 lines
475 B
Plaintext
Altera SOCFPGA SDRAM Error Detection & Correction [EDAC]
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The EDAC accesses a range of registers in the SDRAM controller.
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Required properties:
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- compatible : should contain "altr,sdram-edac" or "altr,sdram-edac-a10"
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- altr,sdr-syscon : phandle of the sdr module
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- interrupts : Should contain the SDRAM ECC IRQ in the
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appropriate format for the IRQ controller.
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Example:
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sdramedac {
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compatible = "altr,sdram-edac";
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altr,sdr-syscon = <&sdr>;
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interrupts = <0 39 4>;
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};
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