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8c05410350
The BF537 SIC combines the gpio port H mask A interrupts with the emac rx interrupt, so we need to demux this in software. It also combines the gpio port H mask B and the emac tx interrupts, and the watchdog and port F mask B interrupts, but since we don't support mask B yet, just add the defines for now. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
217 lines
6.6 KiB
C
217 lines
6.6 KiB
C
/*
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* Copyright 2005-2009 Analog Devices Inc.
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*
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* Licensed under the GPL-2 or later.
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*
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* Set up the interrupt priorities
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*/
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#include <linux/module.h>
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#include <linux/irq.h>
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#include <asm/blackfin.h>
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#include <asm/irq_handler.h>
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#include <asm/bfin5xx_spi.h>
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#include <asm/bfin_sport.h>
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#include <asm/bfin_can.h>
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#include <asm/bfin_dma.h>
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#include <asm/dpmc.h>
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void __init program_IAR(void)
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{
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/* Program the IAR0 Register with the configured priority */
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bfin_write_SIC_IAR0(((CONFIG_IRQ_PLL_WAKEUP - 7) << IRQ_PLL_WAKEUP_POS) |
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((CONFIG_IRQ_DMA_ERROR - 7) << IRQ_DMA_ERROR_POS) |
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((CONFIG_IRQ_ERROR - 7) << IRQ_ERROR_POS) |
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((CONFIG_IRQ_RTC - 7) << IRQ_RTC_POS) |
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((CONFIG_IRQ_PPI - 7) << IRQ_PPI_POS) |
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((CONFIG_IRQ_SPORT0_RX - 7) << IRQ_SPORT0_RX_POS) |
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((CONFIG_IRQ_SPORT0_TX - 7) << IRQ_SPORT0_TX_POS) |
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((CONFIG_IRQ_SPORT1_RX - 7) << IRQ_SPORT1_RX_POS));
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bfin_write_SIC_IAR1(((CONFIG_IRQ_SPORT1_TX - 7) << IRQ_SPORT1_TX_POS) |
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((CONFIG_IRQ_TWI - 7) << IRQ_TWI_POS) |
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((CONFIG_IRQ_SPI - 7) << IRQ_SPI_POS) |
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((CONFIG_IRQ_UART0_RX - 7) << IRQ_UART0_RX_POS) |
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((CONFIG_IRQ_UART0_TX - 7) << IRQ_UART0_TX_POS) |
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((CONFIG_IRQ_UART1_RX - 7) << IRQ_UART1_RX_POS) |
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((CONFIG_IRQ_UART1_TX - 7) << IRQ_UART1_TX_POS) |
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((CONFIG_IRQ_CAN_RX - 7) << IRQ_CAN_RX_POS));
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bfin_write_SIC_IAR2(((CONFIG_IRQ_CAN_TX - 7) << IRQ_CAN_TX_POS) |
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((CONFIG_IRQ_MAC_RX - 7) << IRQ_MAC_RX_POS) |
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((CONFIG_IRQ_MAC_TX - 7) << IRQ_MAC_TX_POS) |
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((CONFIG_IRQ_TIMER0 - 7) << IRQ_TIMER0_POS) |
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((CONFIG_IRQ_TIMER1 - 7) << IRQ_TIMER1_POS) |
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((CONFIG_IRQ_TIMER2 - 7) << IRQ_TIMER2_POS) |
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((CONFIG_IRQ_TIMER3 - 7) << IRQ_TIMER3_POS) |
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((CONFIG_IRQ_TIMER4 - 7) << IRQ_TIMER4_POS));
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bfin_write_SIC_IAR3(((CONFIG_IRQ_TIMER5 - 7) << IRQ_TIMER5_POS) |
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((CONFIG_IRQ_TIMER6 - 7) << IRQ_TIMER6_POS) |
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((CONFIG_IRQ_TIMER7 - 7) << IRQ_TIMER7_POS) |
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((CONFIG_IRQ_PROG_INTA - 7) << IRQ_PROG_INTA_POS) |
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((CONFIG_IRQ_PORTG_INTB - 7) << IRQ_PORTG_INTB_POS) |
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((CONFIG_IRQ_MEM_DMA0 - 7) << IRQ_MEM_DMA0_POS) |
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((CONFIG_IRQ_MEM_DMA1 - 7) << IRQ_MEM_DMA1_POS) |
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((CONFIG_IRQ_WATCH - 7) << IRQ_WATCH_POS));
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SSYNC();
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}
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#define SPI_ERR_MASK (BIT_STAT_TXCOL | BIT_STAT_RBSY | BIT_STAT_MODF | BIT_STAT_TXE) /* SPI_STAT */
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#define SPORT_ERR_MASK (ROVF | RUVF | TOVF | TUVF) /* SPORT_STAT */
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#define PPI_ERR_MASK (0xFFFF & ~FLD) /* PPI_STATUS */
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#define EMAC_ERR_MASK (PHYINT | MMCINT | RXFSINT | TXFSINT | WAKEDET | RXDMAERR | TXDMAERR | STMDONE) /* EMAC_SYSTAT */
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#define UART_ERR_MASK (0x6) /* UART_IIR */
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#define CAN_ERR_MASK (EWTIF | EWRIF | EPIF | BOIF | WUIF | UIAIF | AAIF | RMLIF | UCEIF | EXTIF | ADIF) /* CAN_GIF */
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static int error_int_mask;
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static void bf537_generic_error_mask_irq(struct irq_data *d)
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{
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error_int_mask &= ~(1L << (d->irq - IRQ_PPI_ERROR));
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if (!error_int_mask)
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bfin_internal_mask_irq(IRQ_GENERIC_ERROR);
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}
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static void bf537_generic_error_unmask_irq(struct irq_data *d)
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{
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bfin_internal_unmask_irq(IRQ_GENERIC_ERROR);
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error_int_mask |= 1L << (d->irq - IRQ_PPI_ERROR);
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}
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static struct irq_chip bf537_generic_error_irqchip = {
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.name = "ERROR",
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.irq_ack = bfin_ack_noop,
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.irq_mask_ack = bf537_generic_error_mask_irq,
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.irq_mask = bf537_generic_error_mask_irq,
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.irq_unmask = bf537_generic_error_unmask_irq,
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};
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static void bf537_demux_error_irq(unsigned int int_err_irq,
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struct irq_desc *inta_desc)
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{
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int irq = 0;
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#if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
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if (bfin_read_EMAC_SYSTAT() & EMAC_ERR_MASK)
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irq = IRQ_MAC_ERROR;
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else
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#endif
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if (bfin_read_SPORT0_STAT() & SPORT_ERR_MASK)
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irq = IRQ_SPORT0_ERROR;
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else if (bfin_read_SPORT1_STAT() & SPORT_ERR_MASK)
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irq = IRQ_SPORT1_ERROR;
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else if (bfin_read_PPI_STATUS() & PPI_ERR_MASK)
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irq = IRQ_PPI_ERROR;
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else if (bfin_read_CAN_GIF() & CAN_ERR_MASK)
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irq = IRQ_CAN_ERROR;
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else if (bfin_read_SPI_STAT() & SPI_ERR_MASK)
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irq = IRQ_SPI_ERROR;
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else if ((bfin_read_UART0_IIR() & UART_ERR_MASK) == UART_ERR_MASK)
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irq = IRQ_UART0_ERROR;
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else if ((bfin_read_UART1_IIR() & UART_ERR_MASK) == UART_ERR_MASK)
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irq = IRQ_UART1_ERROR;
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if (irq) {
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if (error_int_mask & (1L << (irq - IRQ_PPI_ERROR)))
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bfin_handle_irq(irq);
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else {
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switch (irq) {
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case IRQ_PPI_ERROR:
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bfin_write_PPI_STATUS(PPI_ERR_MASK);
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break;
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#if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
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case IRQ_MAC_ERROR:
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bfin_write_EMAC_SYSTAT(EMAC_ERR_MASK);
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break;
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#endif
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case IRQ_SPORT0_ERROR:
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bfin_write_SPORT0_STAT(SPORT_ERR_MASK);
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break;
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case IRQ_SPORT1_ERROR:
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bfin_write_SPORT1_STAT(SPORT_ERR_MASK);
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break;
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case IRQ_CAN_ERROR:
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bfin_write_CAN_GIS(CAN_ERR_MASK);
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break;
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case IRQ_SPI_ERROR:
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bfin_write_SPI_STAT(SPI_ERR_MASK);
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break;
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default:
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break;
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}
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pr_debug("IRQ %d:"
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" MASKED PERIPHERAL ERROR INTERRUPT ASSERTED\n",
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irq);
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}
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} else
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pr_err("%s: IRQ ?: PERIPHERAL ERROR INTERRUPT ASSERTED BUT NO SOURCE FOUND\n",
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__func__);
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}
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#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
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static int mac_rx_int_mask;
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static void bf537_mac_rx_mask_irq(struct irq_data *d)
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{
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mac_rx_int_mask &= ~(1L << (d->irq - IRQ_MAC_RX));
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if (!mac_rx_int_mask)
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bfin_internal_mask_irq(IRQ_PH_INTA_MAC_RX);
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}
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static void bf537_mac_rx_unmask_irq(struct irq_data *d)
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{
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bfin_internal_unmask_irq(IRQ_PH_INTA_MAC_RX);
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mac_rx_int_mask |= 1L << (d->irq - IRQ_MAC_RX);
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}
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static struct irq_chip bf537_mac_rx_irqchip = {
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.name = "ERROR",
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.irq_ack = bfin_ack_noop,
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.irq_mask_ack = bf537_mac_rx_mask_irq,
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.irq_mask = bf537_mac_rx_mask_irq,
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.irq_unmask = bf537_mac_rx_unmask_irq,
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};
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static void bf537_demux_mac_rx_irq(unsigned int int_irq,
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struct irq_desc *desc)
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{
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if (bfin_read_DMA1_IRQ_STATUS() & (DMA_DONE | DMA_ERR))
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bfin_handle_irq(IRQ_MAC_RX);
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else
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bfin_demux_gpio_irq(int_irq, desc);
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}
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#endif
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void __init init_mach_irq(void)
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{
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int irq;
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#if defined(CONFIG_BF537) || defined(CONFIG_BF536)
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/* Clear EMAC Interrupt Status bits so we can demux it later */
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bfin_write_EMAC_SYSTAT(-1);
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#endif
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irq_set_chained_handler(IRQ_GENERIC_ERROR, bf537_demux_error_irq);
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for (irq = IRQ_PPI_ERROR; irq <= IRQ_UART1_ERROR; irq++)
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irq_set_chip_and_handler(irq, &bf537_generic_error_irqchip,
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handle_level_irq);
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#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
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irq_set_chained_handler(IRQ_PH_INTA_MAC_RX, bf537_demux_mac_rx_irq);
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irq_set_chip_and_handler(IRQ_MAC_RX, &bf537_mac_rx_irqchip, handle_level_irq);
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irq_set_chip_and_handler(IRQ_PORTH_INTA, &bf537_mac_rx_irqchip, handle_level_irq);
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irq_set_chained_handler(IRQ_MAC_ERROR, bfin_demux_mac_status_irq);
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#endif
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}
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