mirror of
https://github.com/edk2-porting/linux-next.git
synced 2024-12-24 05:04:00 +08:00
e27a9eca5d
This commit fixes a "maybe-uninitialized" build failure in
arch/mips/kvm/tlb.c when KVM, DYNAMIC_DEBUG and JUMP_LABEL are all
enabled. The failure is:
In file included from ./include/linux/printk.h:329:0,
from ./include/linux/kernel.h:13,
from ./include/asm-generic/bug.h:15,
from ./arch/mips/include/asm/bug.h:41,
from ./include/linux/bug.h:4,
from ./include/linux/thread_info.h:11,
from ./include/asm-generic/current.h:4,
from ./arch/mips/include/generated/asm/current.h:1,
from ./include/linux/sched.h:11,
from arch/mips/kvm/tlb.c:13:
arch/mips/kvm/tlb.c: In function ‘kvm_mips_host_tlb_inv’:
./include/linux/dynamic_debug.h:126:3: error: ‘idx_kernel’ may be used uninitialized in this function [-Werror=maybe-uninitialized]
__dynamic_pr_debug(&descriptor, pr_fmt(fmt), \
^~~~~~~~~~~~~~~~~~
arch/mips/kvm/tlb.c:169:16: note: ‘idx_kernel’ was declared here
int idx_user, idx_kernel;
^~~~~~~~~~
There is a similar error relating to "idx_user". Both errors were
observed with GCC 6.
As far as I can tell, it is impossible for either idx_user or idx_kernel
to be uninitialized when they are later read in the calls to kvm_debug,
but to satisfy the compiler, add zero initializers to both variables.
Signed-off-by: James Cowgill <James.Cowgill@imgtec.com>
Fixes: 57e3869cfa
("KVM: MIPS/TLB: Generalise host TLB invalidate to kernel ASID")
Cc: <stable@vger.kernel.org> # 4.11+
Acked-by: James Hogan <james.hogan@imgtec.com>
Signed-off-by: Radim Krčmář <rkrcmar@redhat.com>
661 lines
16 KiB
C
661 lines
16 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* KVM/MIPS TLB handling, this file is part of the Linux host kernel so that
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* TLB handlers run from KSEG0
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*
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* Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
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* Authors: Sanjay Lal <sanjayl@kymasys.com>
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*/
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#include <linux/sched.h>
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#include <linux/smp.h>
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#include <linux/mm.h>
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#include <linux/delay.h>
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#include <linux/export.h>
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#include <linux/kvm_host.h>
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#include <linux/srcu.h>
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#include <asm/cpu.h>
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#include <asm/bootinfo.h>
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#include <asm/mmu_context.h>
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#include <asm/pgtable.h>
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#include <asm/cacheflush.h>
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#include <asm/tlb.h>
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#include <asm/tlbdebug.h>
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#undef CONFIG_MIPS_MT
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#include <asm/r4kcache.h>
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#define CONFIG_MIPS_MT
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#define KVM_GUEST_PC_TLB 0
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#define KVM_GUEST_SP_TLB 1
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#ifdef CONFIG_KVM_MIPS_VZ
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unsigned long GUESTID_MASK;
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EXPORT_SYMBOL_GPL(GUESTID_MASK);
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unsigned long GUESTID_FIRST_VERSION;
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EXPORT_SYMBOL_GPL(GUESTID_FIRST_VERSION);
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unsigned long GUESTID_VERSION_MASK;
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EXPORT_SYMBOL_GPL(GUESTID_VERSION_MASK);
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static u32 kvm_mips_get_root_asid(struct kvm_vcpu *vcpu)
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{
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struct mm_struct *gpa_mm = &vcpu->kvm->arch.gpa_mm;
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if (cpu_has_guestid)
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return 0;
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else
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return cpu_asid(smp_processor_id(), gpa_mm);
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}
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#endif
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static u32 kvm_mips_get_kernel_asid(struct kvm_vcpu *vcpu)
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{
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struct mm_struct *kern_mm = &vcpu->arch.guest_kernel_mm;
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int cpu = smp_processor_id();
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return cpu_asid(cpu, kern_mm);
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}
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static u32 kvm_mips_get_user_asid(struct kvm_vcpu *vcpu)
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{
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struct mm_struct *user_mm = &vcpu->arch.guest_user_mm;
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int cpu = smp_processor_id();
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return cpu_asid(cpu, user_mm);
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}
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/* Structure defining an tlb entry data set. */
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void kvm_mips_dump_host_tlbs(void)
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{
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unsigned long flags;
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local_irq_save(flags);
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kvm_info("HOST TLBs:\n");
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dump_tlb_regs();
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pr_info("\n");
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dump_tlb_all();
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local_irq_restore(flags);
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}
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EXPORT_SYMBOL_GPL(kvm_mips_dump_host_tlbs);
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void kvm_mips_dump_guest_tlbs(struct kvm_vcpu *vcpu)
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{
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struct mips_coproc *cop0 = vcpu->arch.cop0;
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struct kvm_mips_tlb tlb;
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int i;
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kvm_info("Guest TLBs:\n");
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kvm_info("Guest EntryHi: %#lx\n", kvm_read_c0_guest_entryhi(cop0));
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for (i = 0; i < KVM_MIPS_GUEST_TLB_SIZE; i++) {
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tlb = vcpu->arch.guest_tlb[i];
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kvm_info("TLB%c%3d Hi 0x%08lx ",
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(tlb.tlb_lo[0] | tlb.tlb_lo[1]) & ENTRYLO_V
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? ' ' : '*',
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i, tlb.tlb_hi);
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kvm_info("Lo0=0x%09llx %c%c attr %lx ",
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(u64) mips3_tlbpfn_to_paddr(tlb.tlb_lo[0]),
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(tlb.tlb_lo[0] & ENTRYLO_D) ? 'D' : ' ',
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(tlb.tlb_lo[0] & ENTRYLO_G) ? 'G' : ' ',
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(tlb.tlb_lo[0] & ENTRYLO_C) >> ENTRYLO_C_SHIFT);
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kvm_info("Lo1=0x%09llx %c%c attr %lx sz=%lx\n",
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(u64) mips3_tlbpfn_to_paddr(tlb.tlb_lo[1]),
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(tlb.tlb_lo[1] & ENTRYLO_D) ? 'D' : ' ',
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(tlb.tlb_lo[1] & ENTRYLO_G) ? 'G' : ' ',
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(tlb.tlb_lo[1] & ENTRYLO_C) >> ENTRYLO_C_SHIFT,
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tlb.tlb_mask);
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}
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}
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EXPORT_SYMBOL_GPL(kvm_mips_dump_guest_tlbs);
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int kvm_mips_guest_tlb_lookup(struct kvm_vcpu *vcpu, unsigned long entryhi)
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{
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int i;
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int index = -1;
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struct kvm_mips_tlb *tlb = vcpu->arch.guest_tlb;
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for (i = 0; i < KVM_MIPS_GUEST_TLB_SIZE; i++) {
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if (TLB_HI_VPN2_HIT(tlb[i], entryhi) &&
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TLB_HI_ASID_HIT(tlb[i], entryhi)) {
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index = i;
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break;
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}
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}
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kvm_debug("%s: entryhi: %#lx, index: %d lo0: %#lx, lo1: %#lx\n",
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__func__, entryhi, index, tlb[i].tlb_lo[0], tlb[i].tlb_lo[1]);
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return index;
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}
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EXPORT_SYMBOL_GPL(kvm_mips_guest_tlb_lookup);
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static int _kvm_mips_host_tlb_inv(unsigned long entryhi)
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{
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int idx;
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write_c0_entryhi(entryhi);
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mtc0_tlbw_hazard();
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tlb_probe();
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tlb_probe_hazard();
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idx = read_c0_index();
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if (idx >= current_cpu_data.tlbsize)
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BUG();
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if (idx >= 0) {
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write_c0_entryhi(UNIQUE_ENTRYHI(idx));
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write_c0_entrylo0(0);
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write_c0_entrylo1(0);
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mtc0_tlbw_hazard();
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tlb_write_indexed();
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tlbw_use_hazard();
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}
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return idx;
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}
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int kvm_mips_host_tlb_inv(struct kvm_vcpu *vcpu, unsigned long va,
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bool user, bool kernel)
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{
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/*
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* Initialize idx_user and idx_kernel to workaround bogus
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* maybe-initialized warning when using GCC 6.
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*/
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int idx_user = 0, idx_kernel = 0;
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unsigned long flags, old_entryhi;
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local_irq_save(flags);
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old_entryhi = read_c0_entryhi();
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if (user)
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idx_user = _kvm_mips_host_tlb_inv((va & VPN2_MASK) |
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kvm_mips_get_user_asid(vcpu));
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if (kernel)
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idx_kernel = _kvm_mips_host_tlb_inv((va & VPN2_MASK) |
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kvm_mips_get_kernel_asid(vcpu));
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write_c0_entryhi(old_entryhi);
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mtc0_tlbw_hazard();
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local_irq_restore(flags);
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/*
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* We don't want to get reserved instruction exceptions for missing tlb
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* entries.
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*/
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if (cpu_has_vtag_icache)
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flush_icache_all();
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if (user && idx_user >= 0)
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kvm_debug("%s: Invalidated guest user entryhi %#lx @ idx %d\n",
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__func__, (va & VPN2_MASK) |
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kvm_mips_get_user_asid(vcpu), idx_user);
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if (kernel && idx_kernel >= 0)
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kvm_debug("%s: Invalidated guest kernel entryhi %#lx @ idx %d\n",
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__func__, (va & VPN2_MASK) |
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kvm_mips_get_kernel_asid(vcpu), idx_kernel);
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return 0;
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}
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EXPORT_SYMBOL_GPL(kvm_mips_host_tlb_inv);
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#ifdef CONFIG_KVM_MIPS_VZ
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/* GuestID management */
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/**
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* clear_root_gid() - Set GuestCtl1.RID for normal root operation.
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*/
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static inline void clear_root_gid(void)
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{
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if (cpu_has_guestid) {
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clear_c0_guestctl1(MIPS_GCTL1_RID);
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mtc0_tlbw_hazard();
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}
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}
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/**
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* set_root_gid_to_guest_gid() - Set GuestCtl1.RID to match GuestCtl1.ID.
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*
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* Sets the root GuestID to match the current guest GuestID, for TLB operation
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* on the GPA->RPA mappings in the root TLB.
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*
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* The caller must be sure to disable HTW while the root GID is set, and
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* possibly longer if TLB registers are modified.
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*/
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static inline void set_root_gid_to_guest_gid(void)
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{
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unsigned int guestctl1;
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if (cpu_has_guestid) {
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back_to_back_c0_hazard();
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guestctl1 = read_c0_guestctl1();
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guestctl1 = (guestctl1 & ~MIPS_GCTL1_RID) |
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((guestctl1 & MIPS_GCTL1_ID) >> MIPS_GCTL1_ID_SHIFT)
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<< MIPS_GCTL1_RID_SHIFT;
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write_c0_guestctl1(guestctl1);
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mtc0_tlbw_hazard();
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}
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}
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int kvm_vz_host_tlb_inv(struct kvm_vcpu *vcpu, unsigned long va)
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{
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int idx;
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unsigned long flags, old_entryhi;
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local_irq_save(flags);
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htw_stop();
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/* Set root GuestID for root probe and write of guest TLB entry */
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set_root_gid_to_guest_gid();
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old_entryhi = read_c0_entryhi();
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idx = _kvm_mips_host_tlb_inv((va & VPN2_MASK) |
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kvm_mips_get_root_asid(vcpu));
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write_c0_entryhi(old_entryhi);
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clear_root_gid();
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mtc0_tlbw_hazard();
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htw_start();
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local_irq_restore(flags);
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/*
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* We don't want to get reserved instruction exceptions for missing tlb
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* entries.
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*/
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if (cpu_has_vtag_icache)
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flush_icache_all();
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if (idx > 0)
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kvm_debug("%s: Invalidated root entryhi %#lx @ idx %d\n",
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__func__, (va & VPN2_MASK) |
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kvm_mips_get_root_asid(vcpu), idx);
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return 0;
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}
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EXPORT_SYMBOL_GPL(kvm_vz_host_tlb_inv);
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/**
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* kvm_vz_guest_tlb_lookup() - Lookup a guest VZ TLB mapping.
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* @vcpu: KVM VCPU pointer.
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* @gpa: Guest virtual address in a TLB mapped guest segment.
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* @gpa: Ponter to output guest physical address it maps to.
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*
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* Converts a guest virtual address in a guest TLB mapped segment to a guest
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* physical address, by probing the guest TLB.
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*
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* Returns: 0 if guest TLB mapping exists for @gva. *@gpa will have been
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* written.
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* -EFAULT if no guest TLB mapping exists for @gva. *@gpa may not
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* have been written.
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*/
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int kvm_vz_guest_tlb_lookup(struct kvm_vcpu *vcpu, unsigned long gva,
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unsigned long *gpa)
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{
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unsigned long o_entryhi, o_entrylo[2], o_pagemask;
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unsigned int o_index;
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unsigned long entrylo[2], pagemask, pagemaskbit, pa;
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unsigned long flags;
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int index;
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/* Probe the guest TLB for a mapping */
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local_irq_save(flags);
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/* Set root GuestID for root probe of guest TLB entry */
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htw_stop();
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set_root_gid_to_guest_gid();
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o_entryhi = read_gc0_entryhi();
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o_index = read_gc0_index();
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write_gc0_entryhi((o_entryhi & 0x3ff) | (gva & ~0xfffl));
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mtc0_tlbw_hazard();
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guest_tlb_probe();
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tlb_probe_hazard();
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index = read_gc0_index();
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if (index < 0) {
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/* No match, fail */
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write_gc0_entryhi(o_entryhi);
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write_gc0_index(o_index);
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clear_root_gid();
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htw_start();
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local_irq_restore(flags);
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return -EFAULT;
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}
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/* Match! read the TLB entry */
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o_entrylo[0] = read_gc0_entrylo0();
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o_entrylo[1] = read_gc0_entrylo1();
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o_pagemask = read_gc0_pagemask();
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mtc0_tlbr_hazard();
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guest_tlb_read();
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tlb_read_hazard();
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entrylo[0] = read_gc0_entrylo0();
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entrylo[1] = read_gc0_entrylo1();
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pagemask = ~read_gc0_pagemask() & ~0x1fffl;
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write_gc0_entryhi(o_entryhi);
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write_gc0_index(o_index);
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write_gc0_entrylo0(o_entrylo[0]);
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write_gc0_entrylo1(o_entrylo[1]);
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write_gc0_pagemask(o_pagemask);
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clear_root_gid();
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htw_start();
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local_irq_restore(flags);
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/* Select one of the EntryLo values and interpret the GPA */
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pagemaskbit = (pagemask ^ (pagemask & (pagemask - 1))) >> 1;
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pa = entrylo[!!(gva & pagemaskbit)];
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/*
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* TLB entry may have become invalid since TLB probe if physical FTLB
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* entries are shared between threads (e.g. I6400).
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*/
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if (!(pa & ENTRYLO_V))
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return -EFAULT;
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/*
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* Note, this doesn't take guest MIPS32 XPA into account, where PFN is
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* split with XI/RI in the middle.
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*/
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pa = (pa << 6) & ~0xfffl;
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pa |= gva & ~(pagemask | pagemaskbit);
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*gpa = pa;
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return 0;
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}
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EXPORT_SYMBOL_GPL(kvm_vz_guest_tlb_lookup);
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/**
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* kvm_vz_local_flush_roottlb_all_guests() - Flush all root TLB entries for
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* guests.
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*
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* Invalidate all entries in root tlb which are GPA mappings.
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*/
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void kvm_vz_local_flush_roottlb_all_guests(void)
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{
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unsigned long flags;
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unsigned long old_entryhi, old_pagemask, old_guestctl1;
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int entry;
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if (WARN_ON(!cpu_has_guestid))
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return;
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local_irq_save(flags);
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htw_stop();
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/* TLBR may clobber EntryHi.ASID, PageMask, and GuestCtl1.RID */
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old_entryhi = read_c0_entryhi();
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old_pagemask = read_c0_pagemask();
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old_guestctl1 = read_c0_guestctl1();
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/*
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* Invalidate guest entries in root TLB while leaving root entries
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* intact when possible.
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*/
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for (entry = 0; entry < current_cpu_data.tlbsize; entry++) {
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write_c0_index(entry);
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mtc0_tlbw_hazard();
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tlb_read();
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tlb_read_hazard();
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/* Don't invalidate non-guest (RVA) mappings in the root TLB */
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if (!(read_c0_guestctl1() & MIPS_GCTL1_RID))
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continue;
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/* Make sure all entries differ. */
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write_c0_entryhi(UNIQUE_ENTRYHI(entry));
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write_c0_entrylo0(0);
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write_c0_entrylo1(0);
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write_c0_guestctl1(0);
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mtc0_tlbw_hazard();
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tlb_write_indexed();
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}
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write_c0_entryhi(old_entryhi);
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write_c0_pagemask(old_pagemask);
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write_c0_guestctl1(old_guestctl1);
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tlbw_use_hazard();
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htw_start();
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local_irq_restore(flags);
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}
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EXPORT_SYMBOL_GPL(kvm_vz_local_flush_roottlb_all_guests);
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/**
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* kvm_vz_local_flush_guesttlb_all() - Flush all guest TLB entries.
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*
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* Invalidate all entries in guest tlb irrespective of guestid.
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*/
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void kvm_vz_local_flush_guesttlb_all(void)
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{
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unsigned long flags;
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unsigned long old_index;
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unsigned long old_entryhi;
|
|
unsigned long old_entrylo[2];
|
|
unsigned long old_pagemask;
|
|
int entry;
|
|
u64 cvmmemctl2 = 0;
|
|
|
|
local_irq_save(flags);
|
|
|
|
/* Preserve all clobbered guest registers */
|
|
old_index = read_gc0_index();
|
|
old_entryhi = read_gc0_entryhi();
|
|
old_entrylo[0] = read_gc0_entrylo0();
|
|
old_entrylo[1] = read_gc0_entrylo1();
|
|
old_pagemask = read_gc0_pagemask();
|
|
|
|
switch (current_cpu_type()) {
|
|
case CPU_CAVIUM_OCTEON3:
|
|
/* Inhibit machine check due to multiple matching TLB entries */
|
|
cvmmemctl2 = read_c0_cvmmemctl2();
|
|
cvmmemctl2 |= CVMMEMCTL2_INHIBITTS;
|
|
write_c0_cvmmemctl2(cvmmemctl2);
|
|
break;
|
|
};
|
|
|
|
/* Invalidate guest entries in guest TLB */
|
|
write_gc0_entrylo0(0);
|
|
write_gc0_entrylo1(0);
|
|
write_gc0_pagemask(0);
|
|
for (entry = 0; entry < current_cpu_data.guest.tlbsize; entry++) {
|
|
/* Make sure all entries differ. */
|
|
write_gc0_index(entry);
|
|
write_gc0_entryhi(UNIQUE_GUEST_ENTRYHI(entry));
|
|
mtc0_tlbw_hazard();
|
|
guest_tlb_write_indexed();
|
|
}
|
|
|
|
if (cvmmemctl2) {
|
|
cvmmemctl2 &= ~CVMMEMCTL2_INHIBITTS;
|
|
write_c0_cvmmemctl2(cvmmemctl2);
|
|
};
|
|
|
|
write_gc0_index(old_index);
|
|
write_gc0_entryhi(old_entryhi);
|
|
write_gc0_entrylo0(old_entrylo[0]);
|
|
write_gc0_entrylo1(old_entrylo[1]);
|
|
write_gc0_pagemask(old_pagemask);
|
|
tlbw_use_hazard();
|
|
|
|
local_irq_restore(flags);
|
|
}
|
|
EXPORT_SYMBOL_GPL(kvm_vz_local_flush_guesttlb_all);
|
|
|
|
/**
|
|
* kvm_vz_save_guesttlb() - Save a range of guest TLB entries.
|
|
* @buf: Buffer to write TLB entries into.
|
|
* @index: Start index.
|
|
* @count: Number of entries to save.
|
|
*
|
|
* Save a range of guest TLB entries. The caller must ensure interrupts are
|
|
* disabled.
|
|
*/
|
|
void kvm_vz_save_guesttlb(struct kvm_mips_tlb *buf, unsigned int index,
|
|
unsigned int count)
|
|
{
|
|
unsigned int end = index + count;
|
|
unsigned long old_entryhi, old_entrylo0, old_entrylo1, old_pagemask;
|
|
unsigned int guestctl1 = 0;
|
|
int old_index, i;
|
|
|
|
/* Save registers we're about to clobber */
|
|
old_index = read_gc0_index();
|
|
old_entryhi = read_gc0_entryhi();
|
|
old_entrylo0 = read_gc0_entrylo0();
|
|
old_entrylo1 = read_gc0_entrylo1();
|
|
old_pagemask = read_gc0_pagemask();
|
|
|
|
/* Set root GuestID for root probe */
|
|
htw_stop();
|
|
set_root_gid_to_guest_gid();
|
|
if (cpu_has_guestid)
|
|
guestctl1 = read_c0_guestctl1();
|
|
|
|
/* Read each entry from guest TLB */
|
|
for (i = index; i < end; ++i, ++buf) {
|
|
write_gc0_index(i);
|
|
|
|
mtc0_tlbr_hazard();
|
|
guest_tlb_read();
|
|
tlb_read_hazard();
|
|
|
|
if (cpu_has_guestid &&
|
|
(read_c0_guestctl1() ^ guestctl1) & MIPS_GCTL1_RID) {
|
|
/* Entry invalid or belongs to another guest */
|
|
buf->tlb_hi = UNIQUE_GUEST_ENTRYHI(i);
|
|
buf->tlb_lo[0] = 0;
|
|
buf->tlb_lo[1] = 0;
|
|
buf->tlb_mask = 0;
|
|
} else {
|
|
/* Entry belongs to the right guest */
|
|
buf->tlb_hi = read_gc0_entryhi();
|
|
buf->tlb_lo[0] = read_gc0_entrylo0();
|
|
buf->tlb_lo[1] = read_gc0_entrylo1();
|
|
buf->tlb_mask = read_gc0_pagemask();
|
|
}
|
|
}
|
|
|
|
/* Clear root GuestID again */
|
|
clear_root_gid();
|
|
htw_start();
|
|
|
|
/* Restore clobbered registers */
|
|
write_gc0_index(old_index);
|
|
write_gc0_entryhi(old_entryhi);
|
|
write_gc0_entrylo0(old_entrylo0);
|
|
write_gc0_entrylo1(old_entrylo1);
|
|
write_gc0_pagemask(old_pagemask);
|
|
|
|
tlbw_use_hazard();
|
|
}
|
|
EXPORT_SYMBOL_GPL(kvm_vz_save_guesttlb);
|
|
|
|
/**
|
|
* kvm_vz_load_guesttlb() - Save a range of guest TLB entries.
|
|
* @buf: Buffer to read TLB entries from.
|
|
* @index: Start index.
|
|
* @count: Number of entries to load.
|
|
*
|
|
* Load a range of guest TLB entries. The caller must ensure interrupts are
|
|
* disabled.
|
|
*/
|
|
void kvm_vz_load_guesttlb(const struct kvm_mips_tlb *buf, unsigned int index,
|
|
unsigned int count)
|
|
{
|
|
unsigned int end = index + count;
|
|
unsigned long old_entryhi, old_entrylo0, old_entrylo1, old_pagemask;
|
|
int old_index, i;
|
|
|
|
/* Save registers we're about to clobber */
|
|
old_index = read_gc0_index();
|
|
old_entryhi = read_gc0_entryhi();
|
|
old_entrylo0 = read_gc0_entrylo0();
|
|
old_entrylo1 = read_gc0_entrylo1();
|
|
old_pagemask = read_gc0_pagemask();
|
|
|
|
/* Set root GuestID for root probe */
|
|
htw_stop();
|
|
set_root_gid_to_guest_gid();
|
|
|
|
/* Write each entry to guest TLB */
|
|
for (i = index; i < end; ++i, ++buf) {
|
|
write_gc0_index(i);
|
|
write_gc0_entryhi(buf->tlb_hi);
|
|
write_gc0_entrylo0(buf->tlb_lo[0]);
|
|
write_gc0_entrylo1(buf->tlb_lo[1]);
|
|
write_gc0_pagemask(buf->tlb_mask);
|
|
|
|
mtc0_tlbw_hazard();
|
|
guest_tlb_write_indexed();
|
|
}
|
|
|
|
/* Clear root GuestID again */
|
|
clear_root_gid();
|
|
htw_start();
|
|
|
|
/* Restore clobbered registers */
|
|
write_gc0_index(old_index);
|
|
write_gc0_entryhi(old_entryhi);
|
|
write_gc0_entrylo0(old_entrylo0);
|
|
write_gc0_entrylo1(old_entrylo1);
|
|
write_gc0_pagemask(old_pagemask);
|
|
|
|
tlbw_use_hazard();
|
|
}
|
|
EXPORT_SYMBOL_GPL(kvm_vz_load_guesttlb);
|
|
|
|
#endif
|
|
|
|
/**
|
|
* kvm_mips_suspend_mm() - Suspend the active mm.
|
|
* @cpu The CPU we're running on.
|
|
*
|
|
* Suspend the active_mm, ready for a switch to a KVM guest virtual address
|
|
* space. This is left active for the duration of guest context, including time
|
|
* with interrupts enabled, so we need to be careful not to confuse e.g. cache
|
|
* management IPIs.
|
|
*
|
|
* kvm_mips_resume_mm() should be called before context switching to a different
|
|
* process so we don't need to worry about reference counting.
|
|
*
|
|
* This needs to be in static kernel code to avoid exporting init_mm.
|
|
*/
|
|
void kvm_mips_suspend_mm(int cpu)
|
|
{
|
|
cpumask_clear_cpu(cpu, mm_cpumask(current->active_mm));
|
|
current->active_mm = &init_mm;
|
|
}
|
|
EXPORT_SYMBOL_GPL(kvm_mips_suspend_mm);
|
|
|
|
/**
|
|
* kvm_mips_resume_mm() - Resume the current process mm.
|
|
* @cpu The CPU we're running on.
|
|
*
|
|
* Resume the mm of the current process, after a switch back from a KVM guest
|
|
* virtual address space (see kvm_mips_suspend_mm()).
|
|
*/
|
|
void kvm_mips_resume_mm(int cpu)
|
|
{
|
|
cpumask_set_cpu(cpu, mm_cpumask(current->mm));
|
|
current->active_mm = current->mm;
|
|
}
|
|
EXPORT_SYMBOL_GPL(kvm_mips_resume_mm);
|