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36d68f64c4
Krait CPUs have a handful of L2 cache controller registers that live behind a cp15 based indirection register. First you program the indirection register (l2cpselr) to point the L2 'window' register (l2cpdr) at what you want to read/write. Then you read/write the 'window' register to do what you want. The l2cpselr register is not banked per-cpu so we must lock around accesses to it to prevent other CPUs from re-pointing l2cpdr underneath us. Cc: Mark Rutland <mark.rutland@arm.com> Cc: Russell King <linux@arm.linux.org.uk> Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Sricharan R <sricharan@codeaurora.org> Tested-by: Craig Tatlor <ctatlor97@gmail.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
49 lines
1.2 KiB
C
49 lines
1.2 KiB
C
// SPDX-License-Identifier: GPL-2.0
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// Copyright (c) 2018, The Linux Foundation. All rights reserved.
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#include <linux/spinlock.h>
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#include <linux/export.h>
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#include <asm/barrier.h>
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#include <asm/krait-l2-accessors.h>
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static DEFINE_RAW_SPINLOCK(krait_l2_lock);
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void krait_set_l2_indirect_reg(u32 addr, u32 val)
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{
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unsigned long flags;
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raw_spin_lock_irqsave(&krait_l2_lock, flags);
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/*
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* Select the L2 window by poking l2cpselr, then write to the window
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* via l2cpdr.
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*/
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asm volatile ("mcr p15, 3, %0, c15, c0, 6 @ l2cpselr" : : "r" (addr));
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isb();
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asm volatile ("mcr p15, 3, %0, c15, c0, 7 @ l2cpdr" : : "r" (val));
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isb();
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raw_spin_unlock_irqrestore(&krait_l2_lock, flags);
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}
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EXPORT_SYMBOL(krait_set_l2_indirect_reg);
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u32 krait_get_l2_indirect_reg(u32 addr)
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{
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u32 val;
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unsigned long flags;
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raw_spin_lock_irqsave(&krait_l2_lock, flags);
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/*
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* Select the L2 window by poking l2cpselr, then read from the window
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* via l2cpdr.
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*/
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asm volatile ("mcr p15, 3, %0, c15, c0, 6 @ l2cpselr" : : "r" (addr));
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isb();
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asm volatile ("mrc p15, 3, %0, c15, c0, 7 @ l2cpdr" : "=r" (val));
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raw_spin_unlock_irqrestore(&krait_l2_lock, flags);
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return val;
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}
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EXPORT_SYMBOL(krait_get_l2_indirect_reg);
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