Russell King c95680e6f5 ARM: l2c: prima2: remove cache size override ... The cache size should already be present in the L2 cache auxiliary control register: it is part of the integration process to configure the hardware IP. Most platforms get this right, yet still many cargo-cult program, and assume that they always need specifying to the L2 cache code. Remove them so we can find out which really need this. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>		2014-05-30 00:49:53 +01:00
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common.c	ARM: prima2: build reset code standalone	2014-03-17 19:46:12 +01:00
common.h	ARM: prima2: build reset code standalone	2014-03-17 19:46:12 +01:00
headsmp.S	arm: delete __cpuinit/__CPUINIT usage from all ARM users	2013-07-14 19:36:52 -04:00
hotplug.c	ARM: cpu hotplug: remove majority of cache flushing from platforms	2013-04-18 20:08:04 +01:00
Kconfig	Kconfig: rename HAS_IOPORT to HAS_IOPORT_MAP	2014-04-07 16:36:11 -07:00
l2x0.c	ARM: l2c: prima2: remove cache size override	2014-05-30 00:49:53 +01:00
lluart.c	ARM: sirf: enable multiplatform support	2013-03-25 12:29:42 +01:00
Makefile	ARM: sirf: enable multiplatform support	2013-03-25 12:29:42 +01:00
Makefile.boot	ARM: dtb: move all dtb targets to common Makefile	2012-09-20 22:58:17 -07:00
platsmp.c	ARM: prima2: platsmp: fix checkpatch issues	2014-03-05 10:21:20 +08:00
pm.c	ARM: l2c: remove unnecessary call to outer_flush_all()	2014-05-22 16:38:31 +01:00
pm.h	ARM: CSR: PM: add sleep entry for SiRFprimaII	2011-09-21 23:25:59 +08:00
rstc.c	ARM: prima2: build reset code standalone	2014-03-17 19:46:12 +01:00
rtciobrg.c	ARM: prima2: rtciobrg: fix the typo about license	2014-03-05 10:30:23 +08:00
sleep.S	ARM: CSR: PM: add sleep entry for SiRFprimaII	2011-09-21 23:25:59 +08:00