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https://github.com/edk2-porting/linux-next.git
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6098ecb426
Commit ebafed7a ("ARM: irq: Call irqchip_init if no init_irq function is
specified") removed the need to explictly setup the init_irq field in
the machine description when using only irqchip_init. Remove that
declaration for spear as well.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
162 lines
4.8 KiB
C
162 lines
4.8 KiB
C
/*
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* arch/arm/mach-spear13xx/spear1340.c
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*
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* SPEAr1340 machine source file
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*
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* Copyright (C) 2012 ST Microelectronics
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* Viresh Kumar <viresh.linux@gmail.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#define pr_fmt(fmt) "SPEAr1340: " fmt
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#include <linux/ahci_platform.h>
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#include <linux/amba/serial.h>
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#include <linux/delay.h>
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#include <linux/of_platform.h>
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#include <asm/mach/arch.h>
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#include "generic.h"
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#include <mach/spear.h>
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/* FIXME: Move SATA PHY code into a standalone driver */
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/* Base addresses */
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#define SPEAR1340_SATA_BASE UL(0xB1000000)
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/* Power Management Registers */
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#define SPEAR1340_PCM_CFG (VA_MISC_BASE + 0x100)
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#define SPEAR1340_PCM_WKUP_CFG (VA_MISC_BASE + 0x104)
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#define SPEAR1340_SWITCH_CTR (VA_MISC_BASE + 0x108)
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#define SPEAR1340_PERIP1_SW_RST (VA_MISC_BASE + 0x318)
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#define SPEAR1340_PERIP2_SW_RST (VA_MISC_BASE + 0x31C)
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#define SPEAR1340_PERIP3_SW_RST (VA_MISC_BASE + 0x320)
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/* PCIE - SATA configuration registers */
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#define SPEAR1340_PCIE_SATA_CFG (VA_MISC_BASE + 0x424)
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/* PCIE CFG MASks */
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#define SPEAR1340_PCIE_CFG_DEVICE_PRESENT (1 << 11)
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#define SPEAR1340_PCIE_CFG_POWERUP_RESET (1 << 10)
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#define SPEAR1340_PCIE_CFG_CORE_CLK_EN (1 << 9)
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#define SPEAR1340_PCIE_CFG_AUX_CLK_EN (1 << 8)
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#define SPEAR1340_SATA_CFG_TX_CLK_EN (1 << 4)
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#define SPEAR1340_SATA_CFG_RX_CLK_EN (1 << 3)
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#define SPEAR1340_SATA_CFG_POWERUP_RESET (1 << 2)
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#define SPEAR1340_SATA_CFG_PM_CLK_EN (1 << 1)
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#define SPEAR1340_PCIE_SATA_SEL_PCIE (0)
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#define SPEAR1340_PCIE_SATA_SEL_SATA (1)
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#define SPEAR1340_SATA_PCIE_CFG_MASK 0xF1F
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#define SPEAR1340_PCIE_CFG_VAL (SPEAR1340_PCIE_SATA_SEL_PCIE | \
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SPEAR1340_PCIE_CFG_AUX_CLK_EN | \
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SPEAR1340_PCIE_CFG_CORE_CLK_EN | \
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SPEAR1340_PCIE_CFG_POWERUP_RESET | \
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SPEAR1340_PCIE_CFG_DEVICE_PRESENT)
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#define SPEAR1340_SATA_CFG_VAL (SPEAR1340_PCIE_SATA_SEL_SATA | \
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SPEAR1340_SATA_CFG_PM_CLK_EN | \
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SPEAR1340_SATA_CFG_POWERUP_RESET | \
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SPEAR1340_SATA_CFG_RX_CLK_EN | \
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SPEAR1340_SATA_CFG_TX_CLK_EN)
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#define SPEAR1340_PCIE_MIPHY_CFG (VA_MISC_BASE + 0x428)
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#define SPEAR1340_MIPHY_OSC_BYPASS_EXT (1 << 31)
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#define SPEAR1340_MIPHY_CLK_REF_DIV2 (1 << 27)
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#define SPEAR1340_MIPHY_CLK_REF_DIV4 (2 << 27)
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#define SPEAR1340_MIPHY_CLK_REF_DIV8 (3 << 27)
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#define SPEAR1340_MIPHY_PLL_RATIO_TOP(x) (x << 0)
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#define SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA \
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(SPEAR1340_MIPHY_OSC_BYPASS_EXT | \
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SPEAR1340_MIPHY_CLK_REF_DIV2 | \
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SPEAR1340_MIPHY_PLL_RATIO_TOP(60))
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#define SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK \
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(SPEAR1340_MIPHY_PLL_RATIO_TOP(120))
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#define SPEAR1340_PCIE_SATA_MIPHY_CFG_PCIE \
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(SPEAR1340_MIPHY_OSC_BYPASS_EXT | \
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SPEAR1340_MIPHY_PLL_RATIO_TOP(25))
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/* SATA device registration */
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static int sata_miphy_init(struct device *dev, void __iomem *addr)
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{
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writel(SPEAR1340_SATA_CFG_VAL, SPEAR1340_PCIE_SATA_CFG);
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writel(SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK,
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SPEAR1340_PCIE_MIPHY_CFG);
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/* Switch on sata power domain */
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writel((readl(SPEAR1340_PCM_CFG) | (0x800)), SPEAR1340_PCM_CFG);
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msleep(20);
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/* Disable PCIE SATA Controller reset */
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writel((readl(SPEAR1340_PERIP1_SW_RST) & (~0x1000)),
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SPEAR1340_PERIP1_SW_RST);
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msleep(20);
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return 0;
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}
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void sata_miphy_exit(struct device *dev)
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{
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writel(0, SPEAR1340_PCIE_SATA_CFG);
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writel(0, SPEAR1340_PCIE_MIPHY_CFG);
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/* Enable PCIE SATA Controller reset */
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writel((readl(SPEAR1340_PERIP1_SW_RST) | (0x1000)),
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SPEAR1340_PERIP1_SW_RST);
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msleep(20);
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/* Switch off sata power domain */
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writel((readl(SPEAR1340_PCM_CFG) & (~0x800)), SPEAR1340_PCM_CFG);
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msleep(20);
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}
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int sata_suspend(struct device *dev)
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{
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if (dev->power.power_state.event == PM_EVENT_FREEZE)
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return 0;
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sata_miphy_exit(dev);
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return 0;
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}
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int sata_resume(struct device *dev)
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{
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if (dev->power.power_state.event == PM_EVENT_THAW)
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return 0;
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return sata_miphy_init(dev, NULL);
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}
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static struct ahci_platform_data sata_pdata = {
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.init = sata_miphy_init,
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.exit = sata_miphy_exit,
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.suspend = sata_suspend,
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.resume = sata_resume,
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};
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/* Add SPEAr1340 auxdata to pass platform data */
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static struct of_dev_auxdata spear1340_auxdata_lookup[] __initdata = {
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OF_DEV_AUXDATA("snps,spear-ahci", SPEAR1340_SATA_BASE, NULL,
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&sata_pdata),
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{}
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};
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static void __init spear1340_dt_init(void)
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{
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of_platform_populate(NULL, of_default_bus_match_table,
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spear1340_auxdata_lookup, NULL);
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}
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static const char * const spear1340_dt_board_compat[] = {
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"st,spear1340",
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"st,spear1340-evb",
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NULL,
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};
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DT_MACHINE_START(SPEAR1340_DT, "ST SPEAr1340 SoC with Flattened Device Tree")
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.smp = smp_ops(spear13xx_smp_ops),
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.map_io = spear13xx_map_io,
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.init_time = spear13xx_timer_init,
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.init_machine = spear1340_dt_init,
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.restart = spear_restart,
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.dt_compat = spear1340_dt_board_compat,
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MACHINE_END
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