Jon Hunter 9caec6620f clk: tegra210: Fix default rates for HDA clocks ... Currently the default clock rates for the HDA and HDA2CODEC_2X clocks are both 19.2MHz. However, the default rates for these clocks should actually be 51MHz and 48MHz, respectively. The current clock settings results in a distorted output during audio playback. Correct the default clock rates for these clocks by specifying them in the clock init table for Tegra210. Cc: stable@vger.kernel.org Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>		2019-06-14 10:43:38 -07:00
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clk-audio-sync.c	clk: tegra: Fix maximum audio sync clock for Tegra124/210	2018-12-14 13:32:55 -08:00
clk-bpmp.c	clk: tegra: bpmp: Don't crash when a clock fails to register	2018-07-08 16:56:24 -07:00
clk-dfll.c	We have a fairly balanced mix of clk driver updates and clk framework	2019-03-14 08:46:17 -07:00
clk-dfll.h	clk: tegra: dfll: CVB calculation alignment with the regulator	2019-02-06 14:28:41 +01:00
clk-divider.c	clk: tegra: divider: Mark Memory Controller clock as read-only	2019-04-25 13:54:23 -07:00
clk-emc.c	clk: Remove io.h from clk-provider.h	2019-05-15 13:21:37 -07:00
clk-id.h	clk: tegra: make sdmmc2 and sdmmc4 as sdmmc clocks	2018-07-25 14:26:22 -07:00
clk-periph-fixed.c	clk: Remove io.h from clk-provider.h	2019-05-15 13:21:37 -07:00
clk-periph-gate.c	clk: tegra: Fix disable unused for clocks sharing enable bit	2017-03-20 14:13:52 +01:00
clk-periph.c	clk: tegra: Add peripheral clock registration helper	2017-10-19 16:38:40 +02:00
clk-pll-out.c	clk: tegra: Properly include clk.h	2015-07-20 11:11:17 -07:00
clk-pll.c	clk: tegra: Fix PLLM programming on Tegra124+ when PMC overrides divider	2019-04-25 08:17:07 -07:00
clk-sdmmc-mux.c	clk: Remove io.h from clk-provider.h	2019-05-15 13:21:37 -07:00
clk-super.c	clk: tegra: Make tegra_clk_super_mux_ops static	2019-04-11 11:46:02 -07:00
clk-tegra20.c	clk: tegra20: Check whether direct PLLM sourcing is turned off for EMC	2018-11-08 12:47:18 +01:00
clk-tegra30.c	clk: tegra30: Use Tegra CPU powergate helper function	2018-12-14 13:32:55 -08:00
clk-tegra114.c	clk: tegra: Fix maximum audio sync clock for Tegra124/210	2018-12-14 13:32:55 -08:00
clk-tegra124-dfll-fcpu.c	clk: tegra: dfll: Make symbol 'tegra210_cpu_cvb_tables' static	2019-02-18 11:16:22 +01:00
clk-tegra124.c	Merge branches 'clk-stm32f4', 'clk-tegra', 'clk-at91', 'clk-sifive-fu540' and 'clk-spdx' into clk-next	2019-05-07 11:45:29 -07:00
clk-tegra210.c	clk: tegra210: Fix default rates for HDA clocks	2019-06-14 10:43:38 -07:00
clk-tegra-audio.c	clk: tegra: Fix maximum audio sync clock for Tegra124/210	2018-12-14 13:32:55 -08:00
clk-tegra-fixed.c	clk: tegra: Remove trailing blank line	2016-04-28 12:41:45 +02:00
clk-tegra-periph.c	clk: tegra: get rid of duplicate defines	2018-12-14 13:32:54 -08:00
clk-tegra-pmc.c	clk: tegra: Propagate clk_out_x rate to parent	2017-04-04 16:00:28 +02:00
clk-tegra-super-gen4.c	clk: tegra: Mark HCLK, SCLK and EMC as critical	2018-03-12 13:58:58 +01:00
clk-utils.c	clk: tegra: Refactor fractional divider calculation	2018-07-25 13:43:34 -07:00
clk.c	clk: Remove io.h from clk-provider.h	2019-05-15 13:21:37 -07:00
clk.h	clk: tegra: Fix maximum audio sync clock for Tegra124/210	2018-12-14 13:32:55 -08:00
cvb.c	clk: tegra: dfll: CVB calculation alignment with the regulator	2019-02-06 14:28:41 +01:00
cvb.h	clk: tegra: dfll: add CVB tables for Tegra210	2019-02-06 14:29:23 +01:00
Kconfig	clk: tegra: dfll: build clk-dfll.c for Tegra124 and Tegra210	2019-02-06 14:29:37 +01:00
Makefile	clk: tegra: dfll: build clk-dfll.c for Tegra124 and Tegra210	2019-02-06 14:29:37 +01:00