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The snapdragon chips have multiple different display controllers, depending on which chip variant/version. (As far as I can tell, current devices have either MDP3 or MDP4, and upcoming devices have MDSS.) And then external to the display controller are HDMI, DSI, etc. blocks which may be shared across devices which have different display controller blocks. To more easily add support for different display controller blocks, the display controller specific bits are split out into a "kms" module, which provides the kms plane/crtc/encoder objects. The external HDMI, DSI, etc. blocks are part encoder, and part connector currently. But I think I will pull in the drm_bridge patches from chromeos tree, and split them into a bridge+connector, with the registers that need to be set in modeset handled by the bridge. This would remove the 'msm_connector' base class. But some things need to be double checked to make sure I could get the correct ON/OFF sequencing.. This patch adds support for mdp4 crtc (including hw cursor), dtv encoder (part of MDP4 block), and hdmi. Signed-off-by: Rob Clark <robdclark@gmail.com>
70 lines
3.0 KiB
Plaintext
70 lines
3.0 KiB
Plaintext
NOTES about msm drm/kms driver:
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In the current snapdragon SoC's, we have (at least) 3 different
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display controller blocks at play:
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+ MDP3 - ?? seems to be what is on geeksphone peak device
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+ MDP4 - S3 (APQ8060, touchpad), S4-pro (APQ8064, nexus4 & ifc6410)
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+ MDSS - snapdragon 800
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(I don't have a completely clear picture on which display controller
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maps to which part #)
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Plus a handful of blocks around them for HDMI/DSI/etc output.
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And on gpu side of things:
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+ zero, one, or two 2d cores (z180)
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+ and either a2xx or a3xx 3d core.
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But, HDMI/DSI/etc blocks seem like they can be shared across multiple
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display controller blocks. And I for sure don't want to have to deal
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with N different kms devices from xf86-video-freedreno. Plus, it
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seems like we can do some clever tricks like use GPU to trigger
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pageflip after rendering completes (ie. have the kms/crtc code build
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up gpu cmdstream to update scanout and write FLUSH register after).
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So, the approach is one drm driver, with some modularity. Different
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'struct msm_kms' implementations, depending on display controller.
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And one or more 'struct msm_gpu' for the various different gpu sub-
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modules.
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(Second part is not implemented yet. So far this is just basic KMS
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driver, and not exposing any custom ioctls to userspace for now.)
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The kms module provides the plane, crtc, and encoder objects, and
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loads whatever connectors are appropriate.
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For MDP4, the mapping is:
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plane -> PIPE{RGBn,VGn} \
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crtc -> OVLP{n} + DMA{P,S,E} (??) |-> MDP "device"
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encoder -> DTV/LCDC/DSI (within MDP4) /
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connector -> HDMI/DSI/etc --> other device(s)
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Since the irq's that drm core mostly cares about are vblank/framedone,
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we'll let msm_mdp4_kms provide the irq install/uninstall/etc functions
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and treat the MDP4 block's irq as "the" irq. Even though the connectors
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may have their own irqs which they install themselves. For this reason
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the display controller is the "master" device.
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Each connector probably ends up being a separate device, just for the
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logistics of finding/mapping io region, irq, etc. Idealy we would
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have a better way than just stashing the platform device in a global
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(ie. like DT super-node.. but I don't have any snapdragon hw yet that
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is using DT).
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Note that so far I've not been able to get any docs on the hw, and it
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seems that access to such docs would prevent me from working on the
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freedreno gallium driver. So there may be some mistakes in register
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names (I had to invent a few, since no sufficient hint was given in
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the downstream android fbdev driver), bitfield sizes, etc. My current
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state of understanding the registers is given in the envytools rnndb
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files at:
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https://github.com/freedreno/envytools/tree/master/rnndb
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(the mdp4/hdmi/dsi directories)
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These files are used both for a parser tool (in the same tree) to
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parse logged register reads/writes (both from downstream android fbdev
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driver, and this driver with register logging enabled), as well as to
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generate the register level headers.
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