mirror of
https://github.com/edk2-porting/linux-next.git
synced 2024-12-22 20:23:57 +08:00
d861196163
v2: fixes from Russell King:
- include linux/io.h instead of asm/io.h
- fix whitespace in Kconfig
- Use spin_lock_init to initialize lock
- Return -ENOSYS instead of BUG for unimplemented clock ops
- Use proper return values in tegra2 clock ops
additional changes:
- Rename some clocks to match dev_ids
- add rate propagation
- add debugfs entries
- add support for clock listed in clk_lookup under multiple dev_ids
v3:
- Replace per-clock locking with global clock lock
- Autodetect clock state on init
- Let clock dividers pick next lower possible frequency
- Add support for clock init tables
- Minor bug fixes
- Fix checkpatch issues
Signed-off-by: Colin Cross <ccross@android.com>
62 lines
1.6 KiB
C
62 lines
1.6 KiB
C
/*
|
|
* arch/arm/mach-tegra/board-harmony.c
|
|
*
|
|
* Copyright (C) 2010 Google, Inc.
|
|
*
|
|
* Author:
|
|
* Colin Cross <ccross@android.com>
|
|
*
|
|
* This software is licensed under the terms of the GNU General Public
|
|
* License version 2, as published by the Free Software Foundation, and
|
|
* may be copied, distributed, and modified under those terms.
|
|
*
|
|
* This program is distributed in the hope that it will be useful,
|
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
* GNU General Public License for more details.
|
|
*
|
|
*/
|
|
|
|
#include <linux/init.h>
|
|
#include <linux/io.h>
|
|
|
|
#include <asm/hardware/cache-l2x0.h>
|
|
|
|
#include <mach/iomap.h>
|
|
|
|
#include "board.h"
|
|
#include "clock.h"
|
|
|
|
static __initdata struct tegra_clk_init_table common_clk_init_table[] = {
|
|
/* name parent rate enabled */
|
|
{ "clk_m", NULL, 0, true },
|
|
{ "pll_p", "clk_m", 216000000, true },
|
|
{ "pll_p_out1", "pll_p", 28800000, true },
|
|
{ "pll_p_out2", "pll_p", 48000000, true },
|
|
{ "pll_p_out3", "pll_p", 72000000, true },
|
|
{ "pll_p_out4", "pll_p", 108000000, true },
|
|
{ "sys", "pll_p_out4", 108000000, true },
|
|
{ "hclk", "sys", 108000000, true },
|
|
{ "pclk", "hclk", 54000000, true },
|
|
{ NULL, NULL, 0, 0},
|
|
};
|
|
|
|
void __init tegra_init_cache(void)
|
|
{
|
|
#ifdef CONFIG_CACHE_L2X0
|
|
void __iomem *p = IO_ADDRESS(TEGRA_ARM_PERIF_BASE) + 0x3000;
|
|
|
|
writel(0x331, p + L2X0_TAG_LATENCY_CTRL);
|
|
writel(0x441, p + L2X0_DATA_LATENCY_CTRL);
|
|
|
|
l2x0_init(p, 0x6C080001, 0x8200c3fe);
|
|
#endif
|
|
}
|
|
|
|
void __init tegra_common_init(void)
|
|
{
|
|
tegra_init_clock();
|
|
tegra_clk_init_from_table(common_clk_init_table);
|
|
tegra_init_cache();
|
|
}
|