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https://github.com/edk2-porting/linux-next.git
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edff1b4835
The driver is for C-SKY APB bus interrupt controller. It's a simple interrupt controller which use pending reg to detect the irq and use enable/disable reg to mask/unmask interrupt sources. A lot of SOCs based on C-SKY CPU use the interrupt controller as root controller. Signed-off-by: Guo Ren <ren_guo@c-sky.com> Reviewed-by: Mark Rutland <mark.rutland@arm.com>
275 lines
6.7 KiB
C
275 lines
6.7 KiB
C
// SPDX-License-Identifier: GPL-2.0
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// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/module.h>
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#include <linux/irqdomain.h>
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#include <linux/irqchip.h>
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#include <linux/irq.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <asm/irq.h>
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#define INTC_IRQS 64
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#define CK_INTC_ICR 0x00
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#define CK_INTC_PEN31_00 0x14
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#define CK_INTC_PEN63_32 0x2c
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#define CK_INTC_NEN31_00 0x10
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#define CK_INTC_NEN63_32 0x28
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#define CK_INTC_SOURCE 0x40
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#define CK_INTC_DUAL_BASE 0x100
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#define GX_INTC_PEN31_00 0x00
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#define GX_INTC_PEN63_32 0x04
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#define GX_INTC_NEN31_00 0x40
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#define GX_INTC_NEN63_32 0x44
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#define GX_INTC_NMASK31_00 0x50
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#define GX_INTC_NMASK63_32 0x54
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#define GX_INTC_SOURCE 0x60
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static void __iomem *reg_base;
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static struct irq_domain *root_domain;
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static int nr_irq = INTC_IRQS;
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/*
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* When controller support pulse signal, the PEN_reg will hold on signal
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* without software trigger.
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*
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* So, to support pulse signal we need to clear IFR_reg and the address of
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* IFR_offset is NEN_offset - 8.
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*/
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static void irq_ck_mask_set_bit(struct irq_data *d)
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{
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struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
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struct irq_chip_type *ct = irq_data_get_chip_type(d);
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unsigned long ifr = ct->regs.mask - 8;
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u32 mask = d->mask;
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irq_gc_lock(gc);
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*ct->mask_cache |= mask;
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irq_reg_writel(gc, *ct->mask_cache, ct->regs.mask);
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irq_reg_writel(gc, irq_reg_readl(gc, ifr) & ~mask, ifr);
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irq_gc_unlock(gc);
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}
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static void __init ck_set_gc(struct device_node *node, void __iomem *reg_base,
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u32 mask_reg, u32 irq_base)
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{
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struct irq_chip_generic *gc;
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gc = irq_get_domain_generic_chip(root_domain, irq_base);
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gc->reg_base = reg_base;
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gc->chip_types[0].regs.mask = mask_reg;
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gc->chip_types[0].chip.irq_mask = irq_gc_mask_clr_bit;
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gc->chip_types[0].chip.irq_unmask = irq_gc_mask_set_bit;
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if (of_find_property(node, "csky,support-pulse-signal", NULL))
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gc->chip_types[0].chip.irq_unmask = irq_ck_mask_set_bit;
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}
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static inline u32 build_channel_val(u32 idx, u32 magic)
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{
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u32 res;
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/*
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* Set the same index for each channel
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*/
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res = idx | (idx << 8) | (idx << 16) | (idx << 24);
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/*
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* Set the channel magic number in descending order.
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* The magic is 0x00010203 for ck-intc
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* The magic is 0x03020100 for gx6605s-intc
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*/
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return res | magic;
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}
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static inline void setup_irq_channel(u32 magic, void __iomem *reg_addr)
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{
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u32 i;
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/* Setup 64 channel slots */
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for (i = 0; i < INTC_IRQS; i += 4)
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writel_relaxed(build_channel_val(i, magic), reg_addr + i);
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}
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static int __init
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ck_intc_init_comm(struct device_node *node, struct device_node *parent)
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{
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int ret;
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if (parent) {
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pr_err("C-SKY Intc not a root irq controller\n");
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return -EINVAL;
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}
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reg_base = of_iomap(node, 0);
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if (!reg_base) {
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pr_err("C-SKY Intc unable to map: %p.\n", node);
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return -EINVAL;
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}
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root_domain = irq_domain_add_linear(node, nr_irq,
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&irq_generic_chip_ops, NULL);
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if (!root_domain) {
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pr_err("C-SKY Intc irq_domain_add failed.\n");
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return -ENOMEM;
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}
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ret = irq_alloc_domain_generic_chips(root_domain, 32, 1,
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"csky_intc", handle_level_irq,
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IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN, 0, 0);
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if (ret) {
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pr_err("C-SKY Intc irq_alloc_gc failed.\n");
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return -ENOMEM;
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}
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return 0;
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}
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static inline bool handle_irq_perbit(struct pt_regs *regs, u32 hwirq,
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u32 irq_base)
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{
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u32 irq;
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if (hwirq == 0)
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return 0;
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while (hwirq) {
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irq = __ffs(hwirq);
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hwirq &= ~BIT(irq);
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handle_domain_irq(root_domain, irq_base + irq, regs);
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}
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return 1;
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}
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/* gx6605s 64 irqs interrupt controller */
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static void gx_irq_handler(struct pt_regs *regs)
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{
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bool ret;
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do {
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ret = handle_irq_perbit(regs,
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readl_relaxed(reg_base + GX_INTC_PEN31_00), 0);
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ret |= handle_irq_perbit(regs,
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readl_relaxed(reg_base + GX_INTC_PEN63_32), 32);
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} while (ret);
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}
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static int __init
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gx_intc_init(struct device_node *node, struct device_node *parent)
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{
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int ret;
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ret = ck_intc_init_comm(node, parent);
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if (ret)
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return ret;
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/*
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* Initial enable reg to disable all interrupts
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*/
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writel_relaxed(0x0, reg_base + GX_INTC_NEN31_00);
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writel_relaxed(0x0, reg_base + GX_INTC_NEN63_32);
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/*
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* Initial mask reg with all unmasked, because we only use enalbe reg
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*/
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writel_relaxed(0x0, reg_base + GX_INTC_NMASK31_00);
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writel_relaxed(0x0, reg_base + GX_INTC_NMASK63_32);
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setup_irq_channel(0x03020100, reg_base + GX_INTC_SOURCE);
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ck_set_gc(node, reg_base, GX_INTC_NEN31_00, 0);
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ck_set_gc(node, reg_base, GX_INTC_NEN63_32, 32);
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set_handle_irq(gx_irq_handler);
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return 0;
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}
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IRQCHIP_DECLARE(csky_gx6605s_intc, "csky,gx6605s-intc", gx_intc_init);
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/*
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* C-SKY simple 64 irqs interrupt controller, dual-together could support 128
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* irqs.
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*/
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static void ck_irq_handler(struct pt_regs *regs)
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{
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bool ret;
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void __iomem *reg_pen_lo = reg_base + CK_INTC_PEN31_00;
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void __iomem *reg_pen_hi = reg_base + CK_INTC_PEN63_32;
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do {
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/* handle 0 - 31 irqs */
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ret = handle_irq_perbit(regs, readl_relaxed(reg_pen_lo), 0);
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ret |= handle_irq_perbit(regs, readl_relaxed(reg_pen_hi), 32);
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if (nr_irq == INTC_IRQS)
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continue;
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/* handle 64 - 127 irqs */
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ret |= handle_irq_perbit(regs,
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readl_relaxed(reg_pen_lo + CK_INTC_DUAL_BASE), 64);
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ret |= handle_irq_perbit(regs,
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readl_relaxed(reg_pen_hi + CK_INTC_DUAL_BASE), 96);
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} while (ret);
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}
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static int __init
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ck_intc_init(struct device_node *node, struct device_node *parent)
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{
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int ret;
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ret = ck_intc_init_comm(node, parent);
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if (ret)
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return ret;
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/* Initial enable reg to disable all interrupts */
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writel_relaxed(0, reg_base + CK_INTC_NEN31_00);
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writel_relaxed(0, reg_base + CK_INTC_NEN63_32);
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/* Enable irq intc */
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writel_relaxed(BIT(31), reg_base + CK_INTC_ICR);
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ck_set_gc(node, reg_base, CK_INTC_NEN31_00, 0);
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ck_set_gc(node, reg_base, CK_INTC_NEN63_32, 32);
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setup_irq_channel(0x00010203, reg_base + CK_INTC_SOURCE);
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set_handle_irq(ck_irq_handler);
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return 0;
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}
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IRQCHIP_DECLARE(ck_intc, "csky,apb-intc", ck_intc_init);
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static int __init
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ck_dual_intc_init(struct device_node *node, struct device_node *parent)
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{
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int ret;
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/* dual-apb-intc up to 128 irq sources*/
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nr_irq = INTC_IRQS * 2;
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ret = ck_intc_init(node, parent);
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if (ret)
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return ret;
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/* Initial enable reg to disable all interrupts */
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writel_relaxed(0, reg_base + CK_INTC_NEN31_00 + CK_INTC_DUAL_BASE);
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writel_relaxed(0, reg_base + CK_INTC_NEN63_32 + CK_INTC_DUAL_BASE);
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ck_set_gc(node, reg_base + CK_INTC_DUAL_BASE, CK_INTC_NEN31_00, 64);
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ck_set_gc(node, reg_base + CK_INTC_DUAL_BASE, CK_INTC_NEN63_32, 96);
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setup_irq_channel(0x00010203,
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reg_base + CK_INTC_SOURCE + CK_INTC_DUAL_BASE);
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return 0;
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}
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IRQCHIP_DECLARE(ck_dual_intc, "csky,dual-apb-intc", ck_dual_intc_init);
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