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36c9366efd
Add support for Display Update Module and RGB framebuffer device on Philips PNX4008 ARM board. Signed-off-by: Grigory Tolstolytkin <gtolstolytkin@ru.mvista.com> Signed-off-by: Vitaly Wool <vitalywool@gmail.com> Signed-off-by: Antonino Daplas <adaplas@pol.net> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
212 lines
7.4 KiB
C
212 lines
7.4 KiB
C
/*
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* linux/drivers/video/pnx4008/dum.h
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*
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* Internal header for SDUM
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*
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* 2005 (c) Koninklijke Philips N.V. This file is licensed under
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* the terms of the GNU General Public License version 2. This program
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* is licensed "as is" without any warranty of any kind, whether express
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* or implied.
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*/
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#ifndef __PNX008_DUM_H__
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#define __PNX008_DUM_H__
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#include <asm/arch/platform.h>
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#define PNX4008_DUMCONF_VA_BASE IO_ADDRESS(PNX4008_DUMCONF_BASE)
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#define PNX4008_DUM_MAIN_VA_BASE IO_ADDRESS(PNX4008_DUM_MAINCFG_BASE)
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/* DUM CFG ADDRESSES */
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#define DUM_CH_BASE_ADR (PNX4008_DUMCONF_VA_BASE + 0x00)
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#define DUM_CH_MIN_ADR (PNX4008_DUMCONF_VA_BASE + 0x00)
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#define DUM_CH_MAX_ADR (PNX4008_DUMCONF_VA_BASE + 0x04)
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#define DUM_CH_CONF_ADR (PNX4008_DUMCONF_VA_BASE + 0x08)
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#define DUM_CH_STAT_ADR (PNX4008_DUMCONF_VA_BASE + 0x0C)
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#define DUM_CH_CTRL_ADR (PNX4008_DUMCONF_VA_BASE + 0x10)
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#define CH_MARG (0x100 / sizeof(u32))
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#define DUM_CH_MIN(i) (*((volatile u32 *)DUM_CH_MIN_ADR + (i) * CH_MARG))
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#define DUM_CH_MAX(i) (*((volatile u32 *)DUM_CH_MAX_ADR + (i) * CH_MARG))
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#define DUM_CH_CONF(i) (*((volatile u32 *)DUM_CH_CONF_ADR + (i) * CH_MARG))
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#define DUM_CH_STAT(i) (*((volatile u32 *)DUM_CH_STAT_ADR + (i) * CH_MARG))
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#define DUM_CH_CTRL(i) (*((volatile u32 *)DUM_CH_CTRL_ADR + (i) * CH_MARG))
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#define DUM_CONF_ADR (PNX4008_DUM_MAIN_VA_BASE + 0x00)
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#define DUM_CTRL_ADR (PNX4008_DUM_MAIN_VA_BASE + 0x04)
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#define DUM_STAT_ADR (PNX4008_DUM_MAIN_VA_BASE + 0x08)
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#define DUM_DECODE_ADR (PNX4008_DUM_MAIN_VA_BASE + 0x0C)
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#define DUM_COM_BASE_ADR (PNX4008_DUM_MAIN_VA_BASE + 0x10)
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#define DUM_SYNC_C_ADR (PNX4008_DUM_MAIN_VA_BASE + 0x14)
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#define DUM_CLK_DIV_ADR (PNX4008_DUM_MAIN_VA_BASE + 0x18)
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#define DUM_DIRTY_LOW_ADR (PNX4008_DUM_MAIN_VA_BASE + 0x20)
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#define DUM_DIRTY_HIGH_ADR (PNX4008_DUM_MAIN_VA_BASE + 0x24)
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#define DUM_FORMAT_ADR (PNX4008_DUM_MAIN_VA_BASE + 0x28)
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#define DUM_WTCFG1_ADR (PNX4008_DUM_MAIN_VA_BASE + 0x30)
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#define DUM_RTCFG1_ADR (PNX4008_DUM_MAIN_VA_BASE + 0x34)
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#define DUM_WTCFG2_ADR (PNX4008_DUM_MAIN_VA_BASE + 0x38)
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#define DUM_RTCFG2_ADR (PNX4008_DUM_MAIN_VA_BASE + 0x3C)
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#define DUM_TCFG_ADR (PNX4008_DUM_MAIN_VA_BASE + 0x40)
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#define DUM_OUTP_FORMAT1_ADR (PNX4008_DUM_MAIN_VA_BASE + 0x44)
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#define DUM_OUTP_FORMAT2_ADR (PNX4008_DUM_MAIN_VA_BASE + 0x48)
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#define DUM_SYNC_MODE_ADR (PNX4008_DUM_MAIN_VA_BASE + 0x4C)
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#define DUM_SYNC_OUT_C_ADR (PNX4008_DUM_MAIN_VA_BASE + 0x50)
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#define DUM_CONF (*(volatile u32 *)(DUM_CONF_ADR))
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#define DUM_CTRL (*(volatile u32 *)(DUM_CTRL_ADR))
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#define DUM_STAT (*(volatile u32 *)(DUM_STAT_ADR))
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#define DUM_DECODE (*(volatile u32 *)(DUM_DECODE_ADR))
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#define DUM_COM_BASE (*(volatile u32 *)(DUM_COM_BASE_ADR))
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#define DUM_SYNC_C (*(volatile u32 *)(DUM_SYNC_C_ADR))
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#define DUM_CLK_DIV (*(volatile u32 *)(DUM_CLK_DIV_ADR))
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#define DUM_DIRTY_LOW (*(volatile u32 *)(DUM_DIRTY_LOW_ADR))
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#define DUM_DIRTY_HIGH (*(volatile u32 *)(DUM_DIRTY_HIGH_ADR))
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#define DUM_FORMAT (*(volatile u32 *)(DUM_FORMAT_ADR))
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#define DUM_WTCFG1 (*(volatile u32 *)(DUM_WTCFG1_ADR))
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#define DUM_RTCFG1 (*(volatile u32 *)(DUM_RTCFG1_ADR))
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#define DUM_WTCFG2 (*(volatile u32 *)(DUM_WTCFG2_ADR))
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#define DUM_RTCFG2 (*(volatile u32 *)(DUM_RTCFG2_ADR))
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#define DUM_TCFG (*(volatile u32 *)(DUM_TCFG_ADR))
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#define DUM_OUTP_FORMAT1 (*(volatile u32 *)(DUM_OUTP_FORMAT1_ADR))
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#define DUM_OUTP_FORMAT2 (*(volatile u32 *)(DUM_OUTP_FORMAT2_ADR))
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#define DUM_SYNC_MODE (*(volatile u32 *)(DUM_SYNC_MODE_ADR))
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#define DUM_SYNC_OUT_C (*(volatile u32 *)(DUM_SYNC_OUT_C_ADR))
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/* DUM SLAVE ADDRESSES */
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#define DUM_SLAVE_WRITE_ADR (PNX4008_DUM_MAINCFG_BASE + 0x0000000)
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#define DUM_SLAVE_READ1_I_ADR (PNX4008_DUM_MAINCFG_BASE + 0x1000000)
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#define DUM_SLAVE_READ1_R_ADR (PNX4008_DUM_MAINCFG_BASE + 0x1000004)
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#define DUM_SLAVE_READ2_I_ADR (PNX4008_DUM_MAINCFG_BASE + 0x1000008)
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#define DUM_SLAVE_READ2_R_ADR (PNX4008_DUM_MAINCFG_BASE + 0x100000C)
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#define DUM_SLAVE_WRITE_W ((volatile u32 *)(DUM_SLAVE_WRITE_ADR))
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#define DUM_SLAVE_WRITE_HW ((volatile u16 *)(DUM_SLAVE_WRITE_ADR))
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#define DUM_SLAVE_READ1_I ((volatile u8 *)(DUM_SLAVE_READ1_I_ADR))
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#define DUM_SLAVE_READ1_R ((volatile u16 *)(DUM_SLAVE_READ1_R_ADR))
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#define DUM_SLAVE_READ2_I ((volatile u8 *)(DUM_SLAVE_READ2_I_ADR))
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#define DUM_SLAVE_READ2_R ((volatile u16 *)(DUM_SLAVE_READ2_R_ADR))
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/* Sony display register addresses */
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#define DISP_0_REG (0x00)
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#define DISP_1_REG (0x01)
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#define DISP_CAL_REG (0x20)
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#define DISP_ID_REG (0x2A)
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#define DISP_XMIN_L_REG (0x30)
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#define DISP_XMIN_H_REG (0x31)
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#define DISP_YMIN_REG (0x32)
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#define DISP_XMAX_L_REG (0x34)
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#define DISP_XMAX_H_REG (0x35)
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#define DISP_YMAX_REG (0x36)
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#define DISP_SYNC_EN_REG (0x38)
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#define DISP_SYNC_RISE_L_REG (0x3C)
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#define DISP_SYNC_RISE_H_REG (0x3D)
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#define DISP_SYNC_FALL_L_REG (0x3E)
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#define DISP_SYNC_FALL_H_REG (0x3F)
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#define DISP_PIXEL_REG (0x0B)
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#define DISP_DUMMY1_REG (0x28)
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#define DISP_DUMMY2_REG (0x29)
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#define DISP_TIMING_REG (0x98)
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#define DISP_DUMP_REG (0x99)
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/* Sony display constants */
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#define SONY_ID1 (0x22)
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#define SONY_ID2 (0x23)
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/* Philips display register addresses */
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#define PH_DISP_ORIENT_REG (0x003)
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#define PH_DISP_YPOINT_REG (0x200)
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#define PH_DISP_XPOINT_REG (0x201)
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#define PH_DISP_PIXEL_REG (0x202)
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#define PH_DISP_YMIN_REG (0x406)
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#define PH_DISP_YMAX_REG (0x407)
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#define PH_DISP_XMIN_REG (0x408)
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#define PH_DISP_XMAX_REG (0x409)
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/* Misc constants */
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#define NO_VALID_DISPLAY_FOUND (0)
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#define DISPLAY2_IS_NOT_CONNECTED (0)
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/* register values */
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#define V_BAC_ENABLE (BIT(0))
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#define V_BAC_DISABLE_IDLE (BIT(1))
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#define V_BAC_DISABLE_TRIG (BIT(2))
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#define V_DUM_RESET (BIT(3))
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#define V_MUX_RESET (BIT(4))
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#define BAC_ENABLED (BIT(0))
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#define BAC_DISABLED 0
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/* Sony LCD commands */
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#define V_LCD_STANDBY_OFF ((BIT(25)) | (0 << 16) | DISP_0_REG)
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#define V_LCD_USE_9BIT_BUS ((BIT(25)) | (2 << 16) | DISP_1_REG)
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#define V_LCD_SYNC_RISE_L ((BIT(25)) | (0 << 16) | DISP_SYNC_RISE_L_REG)
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#define V_LCD_SYNC_RISE_H ((BIT(25)) | (0 << 16) | DISP_SYNC_RISE_H_REG)
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#define V_LCD_SYNC_FALL_L ((BIT(25)) | (160 << 16) | DISP_SYNC_FALL_L_REG)
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#define V_LCD_SYNC_FALL_H ((BIT(25)) | (0 << 16) | DISP_SYNC_FALL_H_REG)
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#define V_LCD_SYNC_ENABLE ((BIT(25)) | (128 << 16) | DISP_SYNC_EN_REG)
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#define V_LCD_DISPLAY_ON ((BIT(25)) | (64 << 16) | DISP_0_REG)
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enum {
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PAD_NONE,
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PAD_512,
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PAD_1024
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};
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enum {
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RGB888,
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RGB666,
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RGB565,
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BGR565,
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ARGB1555,
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ABGR1555,
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ARGB4444,
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ABGR4444
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};
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struct dum_setup {
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int sync_neg_edge;
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int round_robin;
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int mux_int;
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int synced_dirty_flag_int;
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int dirty_flag_int;
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int error_int;
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int pf_empty_int;
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int sf_empty_int;
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int bac_dis_int;
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u32 dirty_base_adr;
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u32 command_base_adr;
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u32 sync_clk_div;
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int sync_output;
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u32 sync_restart_val;
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u32 set_sync_high;
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u32 set_sync_low;
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};
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struct dum_ch_setup {
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int disp_no;
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u32 xmin;
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u32 ymin;
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u32 xmax;
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u32 ymax;
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int xmirror;
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int ymirror;
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int rotate;
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u32 minadr;
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u32 maxadr;
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u32 dirtybuffer;
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int pad;
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int format;
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int hwdirty;
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int slave_trans;
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};
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struct disp_window {
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u32 xmin_l;
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u32 xmin_h;
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u32 ymin;
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u32 xmax_l;
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u32 xmax_h;
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u32 ymax;
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};
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#endif /* #ifndef __PNX008_DUM_H__ */
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