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9a8fd55899
The attached patches provides part 6 of an architecture implementation for the Tensilica Xtensa CPU series. Signed-off-by: Chris Zankel <chris@zankel.net> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
24 lines
589 B
C
24 lines
589 B
C
/*
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* include/asm-xtensa/shmparam.h
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*
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* This file is subject to the terms and conditions of the GNU General
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* Public License. See the file "COPYING" in the main directory of
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* this archive for more details.
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*/
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#ifndef _XTENSA_SHMPARAM_H
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#define _XTENSA_SHMPARAM_H
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#include <asm/processor.h>
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/*
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* Xtensa can have variable size caches, and if
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* the size of single way is larger than the page size,
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* then we have to start worrying about cache aliasing
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* problems.
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*/
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#define SHMLBA ((PAGE_SIZE > DCACHE_WAY_SIZE)? PAGE_SIZE : DCACHE_WAY_SIZE)
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#endif /* _XTENSA_SHMPARAM_H */
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