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177cf6e52b
All the clocksource drivers's init function are now converted to return an error code. CLOCKSOURCE_OF_DECLARE is no longer used as well as the clksrc-of table. Let's convert back the names: - CLOCKSOURCE_OF_DECLARE_RET => CLOCKSOURCE_OF_DECLARE - clksrc-of-ret => clksrc-of Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> For exynos_mct and samsung_pwm_timer: Acked-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> For arch/arc: Acked-by: Vineet Gupta <vgupta@synopsys.com> For mediatek driver: Acked-by: Matthias Brugger <matthias.bgg@gmail.com> For the Rockchip-part Acked-by: Heiko Stuebner <heiko@sntech.de> For STi : Acked-by: Patrice Chotard <patrice.chotard@st.com> For the mps2-timer.c and versatile.c changes: Acked-by: Liviu Dudau <Liviu.Dudau@arm.com> For the OXNAS part : Acked-by: Neil Armstrong <narmstrong@baylibre.com> For LPC32xx driver: Acked-by: Sylvain Lemieux <slemieux.tyco@gmail.com> For Broadcom Kona timer change: Acked-by: Ray Jui <ray.jui@broadcom.com> For Sun4i and Sun5i: Acked-by: Chen-Yu Tsai <wens@csie.org> For Meson6: Acked-by: Carlo Caione <carlo@caione.org> For Keystone: Acked-by: Santosh Shilimkar <ssantosh@kernel.org> For NPS: Acked-by: Noam Camus <noamca@mellanox.com> For bcm2835: Acked-by: Eric Anholt <eric@anholt.net>
91 lines
2.5 KiB
C
91 lines
2.5 KiB
C
/*
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* Copyright (C) ST-Ericsson SA 2011
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*
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* License Terms: GNU General Public License v2
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* Author: Mattias Wallin <mattias.wallin@stericsson.com> for ST-Ericsson
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* Author: Sundar Iyer for ST-Ericsson
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* sched_clock implementation is based on:
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* plat-nomadik/timer.c Linus Walleij <linus.walleij@stericsson.com>
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*
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* DBx500-PRCMU Timer
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* The PRCMU has 5 timers which are available in a always-on
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* power domain. We use the Timer 4 for our always-on clock
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* source on DB8500.
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*/
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/clockchips.h>
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#include <linux/sched_clock.h>
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#define RATE_32K 32768
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#define TIMER_MODE_CONTINOUS 0x1
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#define TIMER_DOWNCOUNT_VAL 0xffffffff
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#define PRCMU_TIMER_REF 0
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#define PRCMU_TIMER_DOWNCOUNT 0x4
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#define PRCMU_TIMER_MODE 0x8
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#define SCHED_CLOCK_MIN_WRAP 131072 /* 2^32 / 32768 */
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static void __iomem *clksrc_dbx500_timer_base;
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static cycle_t notrace clksrc_dbx500_prcmu_read(struct clocksource *cs)
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{
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void __iomem *base = clksrc_dbx500_timer_base;
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u32 count, count2;
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do {
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count = readl_relaxed(base + PRCMU_TIMER_DOWNCOUNT);
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count2 = readl_relaxed(base + PRCMU_TIMER_DOWNCOUNT);
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} while (count2 != count);
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/* Negate because the timer is a decrementing counter */
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return ~count;
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}
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static struct clocksource clocksource_dbx500_prcmu = {
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.name = "dbx500-prcmu-timer",
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.rating = 300,
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.read = clksrc_dbx500_prcmu_read,
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.mask = CLOCKSOURCE_MASK(32),
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.flags = CLOCK_SOURCE_IS_CONTINUOUS,
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};
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#ifdef CONFIG_CLKSRC_DBX500_PRCMU_SCHED_CLOCK
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static u64 notrace dbx500_prcmu_sched_clock_read(void)
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{
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if (unlikely(!clksrc_dbx500_timer_base))
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return 0;
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return clksrc_dbx500_prcmu_read(&clocksource_dbx500_prcmu);
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}
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#endif
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static int __init clksrc_dbx500_prcmu_init(struct device_node *node)
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{
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clksrc_dbx500_timer_base = of_iomap(node, 0);
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/*
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* The A9 sub system expects the timer to be configured as
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* a continous looping timer.
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* The PRCMU should configure it but if it for some reason
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* don't we do it here.
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*/
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if (readl(clksrc_dbx500_timer_base + PRCMU_TIMER_MODE) !=
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TIMER_MODE_CONTINOUS) {
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writel(TIMER_MODE_CONTINOUS,
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clksrc_dbx500_timer_base + PRCMU_TIMER_MODE);
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writel(TIMER_DOWNCOUNT_VAL,
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clksrc_dbx500_timer_base + PRCMU_TIMER_REF);
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}
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#ifdef CONFIG_CLKSRC_DBX500_PRCMU_SCHED_CLOCK
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sched_clock_register(dbx500_prcmu_sched_clock_read, 32, RATE_32K);
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#endif
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return clocksource_register_hz(&clocksource_dbx500_prcmu, RATE_32K);
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}
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CLOCKSOURCE_OF_DECLARE(dbx500_prcmu, "stericsson,db8500-prcmu-timer-4",
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clksrc_dbx500_prcmu_init);
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