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d2912cb15b
Based on 2 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation # extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 4122 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Enrico Weigelt <info@metux.net> Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190604081206.933168790@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
445 lines
9.8 KiB
C
445 lines
9.8 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2011 Texas Instruments Incorporated
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* Author: Mark Salter <msalter@redhat.com>
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*/
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/io.h>
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#include <asm/cache.h>
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#include <asm/soc.h>
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/*
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* Internal Memory Control Registers for caches
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*/
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#define IMCR_CCFG 0x0000
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#define IMCR_L1PCFG 0x0020
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#define IMCR_L1PCC 0x0024
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#define IMCR_L1DCFG 0x0040
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#define IMCR_L1DCC 0x0044
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#define IMCR_L2ALLOC0 0x2000
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#define IMCR_L2ALLOC1 0x2004
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#define IMCR_L2ALLOC2 0x2008
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#define IMCR_L2ALLOC3 0x200c
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#define IMCR_L2WBAR 0x4000
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#define IMCR_L2WWC 0x4004
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#define IMCR_L2WIBAR 0x4010
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#define IMCR_L2WIWC 0x4014
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#define IMCR_L2IBAR 0x4018
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#define IMCR_L2IWC 0x401c
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#define IMCR_L1PIBAR 0x4020
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#define IMCR_L1PIWC 0x4024
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#define IMCR_L1DWIBAR 0x4030
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#define IMCR_L1DWIWC 0x4034
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#define IMCR_L1DWBAR 0x4040
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#define IMCR_L1DWWC 0x4044
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#define IMCR_L1DIBAR 0x4048
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#define IMCR_L1DIWC 0x404c
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#define IMCR_L2WB 0x5000
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#define IMCR_L2WBINV 0x5004
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#define IMCR_L2INV 0x5008
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#define IMCR_L1PINV 0x5028
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#define IMCR_L1DWB 0x5040
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#define IMCR_L1DWBINV 0x5044
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#define IMCR_L1DINV 0x5048
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#define IMCR_MAR_BASE 0x8000
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#define IMCR_MAR96_111 0x8180
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#define IMCR_MAR128_191 0x8200
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#define IMCR_MAR224_239 0x8380
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#define IMCR_L2MPFAR 0xa000
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#define IMCR_L2MPFSR 0xa004
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#define IMCR_L2MPFCR 0xa008
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#define IMCR_L2MPLK0 0xa100
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#define IMCR_L2MPLK1 0xa104
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#define IMCR_L2MPLK2 0xa108
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#define IMCR_L2MPLK3 0xa10c
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#define IMCR_L2MPLKCMD 0xa110
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#define IMCR_L2MPLKSTAT 0xa114
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#define IMCR_L2MPPA_BASE 0xa200
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#define IMCR_L1PMPFAR 0xa400
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#define IMCR_L1PMPFSR 0xa404
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#define IMCR_L1PMPFCR 0xa408
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#define IMCR_L1PMPLK0 0xa500
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#define IMCR_L1PMPLK1 0xa504
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#define IMCR_L1PMPLK2 0xa508
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#define IMCR_L1PMPLK3 0xa50c
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#define IMCR_L1PMPLKCMD 0xa510
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#define IMCR_L1PMPLKSTAT 0xa514
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#define IMCR_L1PMPPA_BASE 0xa600
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#define IMCR_L1DMPFAR 0xac00
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#define IMCR_L1DMPFSR 0xac04
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#define IMCR_L1DMPFCR 0xac08
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#define IMCR_L1DMPLK0 0xad00
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#define IMCR_L1DMPLK1 0xad04
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#define IMCR_L1DMPLK2 0xad08
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#define IMCR_L1DMPLK3 0xad0c
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#define IMCR_L1DMPLKCMD 0xad10
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#define IMCR_L1DMPLKSTAT 0xad14
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#define IMCR_L1DMPPA_BASE 0xae00
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#define IMCR_L2PDWAKE0 0xc040
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#define IMCR_L2PDWAKE1 0xc044
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#define IMCR_L2PDSLEEP0 0xc050
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#define IMCR_L2PDSLEEP1 0xc054
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#define IMCR_L2PDSTAT0 0xc060
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#define IMCR_L2PDSTAT1 0xc064
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/*
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* CCFG register values and bits
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*/
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#define L2MODE_0K_CACHE 0x0
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#define L2MODE_32K_CACHE 0x1
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#define L2MODE_64K_CACHE 0x2
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#define L2MODE_128K_CACHE 0x3
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#define L2MODE_256K_CACHE 0x7
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#define L2PRIO_URGENT 0x0
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#define L2PRIO_HIGH 0x1
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#define L2PRIO_MEDIUM 0x2
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#define L2PRIO_LOW 0x3
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#define CCFG_ID 0x100 /* Invalidate L1P bit */
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#define CCFG_IP 0x200 /* Invalidate L1D bit */
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static void __iomem *cache_base;
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/*
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* L1 & L2 caches generic functions
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*/
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#define imcr_get(reg) soc_readl(cache_base + (reg))
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#define imcr_set(reg, value) \
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do { \
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soc_writel((value), cache_base + (reg)); \
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soc_readl(cache_base + (reg)); \
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} while (0)
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static void cache_block_operation_wait(unsigned int wc_reg)
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{
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/* Wait for completion */
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while (imcr_get(wc_reg))
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cpu_relax();
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}
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static DEFINE_SPINLOCK(cache_lock);
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/*
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* Generic function to perform a block cache operation as
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* invalidate or writeback/invalidate
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*/
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static void cache_block_operation(unsigned int *start,
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unsigned int *end,
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unsigned int bar_reg,
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unsigned int wc_reg)
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{
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unsigned long flags;
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unsigned int wcnt =
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(L2_CACHE_ALIGN_CNT((unsigned int) end)
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- L2_CACHE_ALIGN_LOW((unsigned int) start)) >> 2;
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unsigned int wc = 0;
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for (; wcnt; wcnt -= wc, start += wc) {
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loop:
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spin_lock_irqsave(&cache_lock, flags);
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/*
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* If another cache operation is occurring
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*/
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if (unlikely(imcr_get(wc_reg))) {
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spin_unlock_irqrestore(&cache_lock, flags);
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/* Wait for previous operation completion */
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cache_block_operation_wait(wc_reg);
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/* Try again */
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goto loop;
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}
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imcr_set(bar_reg, L2_CACHE_ALIGN_LOW((unsigned int) start));
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if (wcnt > 0xffff)
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wc = 0xffff;
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else
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wc = wcnt;
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/* Set word count value in the WC register */
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imcr_set(wc_reg, wc & 0xffff);
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spin_unlock_irqrestore(&cache_lock, flags);
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/* Wait for completion */
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cache_block_operation_wait(wc_reg);
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}
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}
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static void cache_block_operation_nowait(unsigned int *start,
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unsigned int *end,
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unsigned int bar_reg,
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unsigned int wc_reg)
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{
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unsigned long flags;
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unsigned int wcnt =
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(L2_CACHE_ALIGN_CNT((unsigned int) end)
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- L2_CACHE_ALIGN_LOW((unsigned int) start)) >> 2;
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unsigned int wc = 0;
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for (; wcnt; wcnt -= wc, start += wc) {
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spin_lock_irqsave(&cache_lock, flags);
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imcr_set(bar_reg, L2_CACHE_ALIGN_LOW((unsigned int) start));
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if (wcnt > 0xffff)
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wc = 0xffff;
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else
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wc = wcnt;
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/* Set word count value in the WC register */
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imcr_set(wc_reg, wc & 0xffff);
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spin_unlock_irqrestore(&cache_lock, flags);
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/* Don't wait for completion on last cache operation */
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if (wcnt > 0xffff)
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cache_block_operation_wait(wc_reg);
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}
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}
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/*
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* L1 caches management
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*/
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/*
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* Disable L1 caches
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*/
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void L1_cache_off(void)
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{
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unsigned int dummy;
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imcr_set(IMCR_L1PCFG, 0);
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dummy = imcr_get(IMCR_L1PCFG);
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imcr_set(IMCR_L1DCFG, 0);
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dummy = imcr_get(IMCR_L1DCFG);
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}
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/*
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* Enable L1 caches
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*/
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void L1_cache_on(void)
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{
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unsigned int dummy;
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imcr_set(IMCR_L1PCFG, 7);
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dummy = imcr_get(IMCR_L1PCFG);
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imcr_set(IMCR_L1DCFG, 7);
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dummy = imcr_get(IMCR_L1DCFG);
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}
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/*
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* L1P global-invalidate all
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*/
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void L1P_cache_global_invalidate(void)
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{
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unsigned int set = 1;
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imcr_set(IMCR_L1PINV, set);
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while (imcr_get(IMCR_L1PINV) & 1)
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cpu_relax();
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}
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/*
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* L1D global-invalidate all
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*
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* Warning: this operation causes all updated data in L1D to
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* be discarded rather than written back to the lower levels of
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* memory
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*/
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void L1D_cache_global_invalidate(void)
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{
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unsigned int set = 1;
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imcr_set(IMCR_L1DINV, set);
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while (imcr_get(IMCR_L1DINV) & 1)
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cpu_relax();
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}
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void L1D_cache_global_writeback(void)
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{
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unsigned int set = 1;
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imcr_set(IMCR_L1DWB, set);
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while (imcr_get(IMCR_L1DWB) & 1)
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cpu_relax();
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}
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void L1D_cache_global_writeback_invalidate(void)
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{
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unsigned int set = 1;
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imcr_set(IMCR_L1DWBINV, set);
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while (imcr_get(IMCR_L1DWBINV) & 1)
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cpu_relax();
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}
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/*
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* L2 caches management
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*/
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/*
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* Set L2 operation mode
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*/
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void L2_cache_set_mode(unsigned int mode)
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{
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unsigned int ccfg = imcr_get(IMCR_CCFG);
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/* Clear and set the L2MODE bits in CCFG */
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ccfg &= ~7;
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ccfg |= (mode & 7);
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imcr_set(IMCR_CCFG, ccfg);
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ccfg = imcr_get(IMCR_CCFG);
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}
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/*
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* L2 global-writeback and global-invalidate all
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*/
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void L2_cache_global_writeback_invalidate(void)
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{
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imcr_set(IMCR_L2WBINV, 1);
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while (imcr_get(IMCR_L2WBINV))
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cpu_relax();
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}
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/*
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* L2 global-writeback all
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*/
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void L2_cache_global_writeback(void)
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{
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imcr_set(IMCR_L2WB, 1);
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while (imcr_get(IMCR_L2WB))
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cpu_relax();
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}
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/*
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* Cacheability controls
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*/
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void enable_caching(unsigned long start, unsigned long end)
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{
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unsigned int mar = IMCR_MAR_BASE + ((start >> 24) << 2);
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unsigned int mar_e = IMCR_MAR_BASE + ((end >> 24) << 2);
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for (; mar <= mar_e; mar += 4)
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imcr_set(mar, imcr_get(mar) | 1);
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}
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void disable_caching(unsigned long start, unsigned long end)
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{
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unsigned int mar = IMCR_MAR_BASE + ((start >> 24) << 2);
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unsigned int mar_e = IMCR_MAR_BASE + ((end >> 24) << 2);
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for (; mar <= mar_e; mar += 4)
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imcr_set(mar, imcr_get(mar) & ~1);
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}
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/*
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* L1 block operations
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*/
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void L1P_cache_block_invalidate(unsigned int start, unsigned int end)
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{
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cache_block_operation((unsigned int *) start,
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(unsigned int *) end,
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IMCR_L1PIBAR, IMCR_L1PIWC);
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}
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EXPORT_SYMBOL(L1P_cache_block_invalidate);
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void L1D_cache_block_invalidate(unsigned int start, unsigned int end)
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{
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cache_block_operation((unsigned int *) start,
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(unsigned int *) end,
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IMCR_L1DIBAR, IMCR_L1DIWC);
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}
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void L1D_cache_block_writeback_invalidate(unsigned int start, unsigned int end)
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{
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cache_block_operation((unsigned int *) start,
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(unsigned int *) end,
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IMCR_L1DWIBAR, IMCR_L1DWIWC);
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}
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void L1D_cache_block_writeback(unsigned int start, unsigned int end)
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{
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cache_block_operation((unsigned int *) start,
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(unsigned int *) end,
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IMCR_L1DWBAR, IMCR_L1DWWC);
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}
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EXPORT_SYMBOL(L1D_cache_block_writeback);
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/*
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* L2 block operations
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*/
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void L2_cache_block_invalidate(unsigned int start, unsigned int end)
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{
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cache_block_operation((unsigned int *) start,
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(unsigned int *) end,
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IMCR_L2IBAR, IMCR_L2IWC);
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}
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void L2_cache_block_writeback(unsigned int start, unsigned int end)
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{
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cache_block_operation((unsigned int *) start,
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(unsigned int *) end,
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IMCR_L2WBAR, IMCR_L2WWC);
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}
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void L2_cache_block_writeback_invalidate(unsigned int start, unsigned int end)
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{
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cache_block_operation((unsigned int *) start,
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(unsigned int *) end,
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IMCR_L2WIBAR, IMCR_L2WIWC);
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}
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void L2_cache_block_invalidate_nowait(unsigned int start, unsigned int end)
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{
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cache_block_operation_nowait((unsigned int *) start,
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(unsigned int *) end,
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IMCR_L2IBAR, IMCR_L2IWC);
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}
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void L2_cache_block_writeback_nowait(unsigned int start, unsigned int end)
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{
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cache_block_operation_nowait((unsigned int *) start,
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(unsigned int *) end,
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IMCR_L2WBAR, IMCR_L2WWC);
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}
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void L2_cache_block_writeback_invalidate_nowait(unsigned int start,
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unsigned int end)
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{
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cache_block_operation_nowait((unsigned int *) start,
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(unsigned int *) end,
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IMCR_L2WIBAR, IMCR_L2WIWC);
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}
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/*
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* L1 and L2 caches configuration
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*/
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void __init c6x_cache_init(void)
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{
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struct device_node *node;
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node = of_find_compatible_node(NULL, NULL, "ti,c64x+cache");
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if (!node)
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return;
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cache_base = of_iomap(node, 0);
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of_node_put(node);
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if (!cache_base)
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return;
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/* Set L2 caches on the the whole L2 SRAM memory */
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L2_cache_set_mode(L2MODE_SIZE);
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/* Enable L1 */
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L1_cache_on();
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}
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