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078a55fc82
commit 3747069b25e419f6b51395f48127e9812abc3596 upstream.
The __cpuinit type of throwaway sections might have made sense
some time ago when RAM was more constrained, but now the savings
do not offset the cost and complications. For example, the fix in
commit 5e427ec2d0 ("x86: Fix bit corruption at CPU resume time")
is a good example of the nasty type of bugs that can be created
with improper use of the various __init prefixes.
After a discussion on LKML[1] it was decided that cpuinit should go
the way of devinit and be phased out. Once all the users are gone,
we can then finally remove the macros themselves from linux/init.h.
Note that some harmless section mismatch warnings may result, since
notify_cpu_starting() and cpu_up() are arch independent (kernel/cpu.c)
and are flagged as __cpuinit -- so if we remove the __cpuinit from
the arch specific callers, we will also get section mismatch warnings.
As an intermediate step, we intend to turn the linux/init.h cpuinit
related content into no-ops as early as possible, since that will get
rid of these warnings. In any case, they are temporary and harmless.
Here, we remove all the MIPS __cpuinit from C code and __CPUINIT
from asm files. MIPS is interesting in this respect, because there
are also uasm users hiding behind their own renamed versions of the
__cpuinit macros.
[1] https://lkml.org/lkml/2013/5/20/589
[ralf@linux-mips.org: Folded in Paul's followup fix.]
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/5494/
Patchwork: https://patchwork.linux-mips.org/patch/5495/
Patchwork: https://patchwork.linux-mips.org/patch/5509/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
140 lines
4.1 KiB
ArmAsm
140 lines
4.1 KiB
ArmAsm
/*
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* Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
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* reserved.
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the NetLogic
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* license below:
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
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* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
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* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <linux/init.h>
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#include <asm/asm.h>
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#include <asm/asm-offsets.h>
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#include <asm/regdef.h>
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#include <asm/mipsregs.h>
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#include <asm/stackframe.h>
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#include <asm/asmmacro.h>
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#include <asm/addrspace.h>
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#include <asm/netlogic/common.h>
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#include <asm/netlogic/xlp-hal/iomap.h>
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#include <asm/netlogic/xlp-hal/xlp.h>
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#include <asm/netlogic/xlp-hal/sys.h>
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#include <asm/netlogic/xlp-hal/cpucontrol.h>
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#define CP0_EBASE $15
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.set noreorder
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.set noat
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.set arch=xlr /* for mfcr/mtcr, XLR is sufficient */
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FEXPORT(xlp_boot_core0_siblings) /* "Master" cpu starts from here */
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dmtc0 sp, $4, 2 /* SP saved in UserLocal */
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SAVE_ALL
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sync
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/* find the location to which nlm_boot_siblings was relocated */
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li t0, CKSEG1ADDR(RESET_VEC_PHYS)
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dla t1, nlm_reset_entry
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dla t2, nlm_boot_siblings
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dsubu t2, t1
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daddu t2, t0
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/* call it */
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jr t2
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nop
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/* not reached */
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NESTED(nlm_boot_secondary_cpus, 16, sp)
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/* Initialize CP0 Status */
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move t1, zero
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#ifdef CONFIG_64BIT
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ori t1, ST0_KX
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#endif
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mtc0 t1, CP0_STATUS
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PTR_LA t1, nlm_next_sp
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PTR_L sp, 0(t1)
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PTR_LA t1, nlm_next_gp
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PTR_L gp, 0(t1)
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/* a0 has the processor id */
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mfc0 a0, CP0_EBASE, 1
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andi a0, 0x3ff /* a0 <- node/core */
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PTR_LA t0, nlm_early_init_secondary
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jalr t0
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nop
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PTR_LA t0, smp_bootstrap
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jr t0
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nop
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END(nlm_boot_secondary_cpus)
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/*
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* In case of RMIboot bootloader which is used on XLR boards, the CPUs
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* be already woken up and waiting in bootloader code.
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* This will get them out of the bootloader code and into linux. Needed
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* because the bootloader area will be taken and initialized by linux.
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*/
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NESTED(nlm_rmiboot_preboot, 16, sp)
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mfc0 t0, $15, 1 /* read ebase */
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andi t0, 0x1f /* t0 has the processor_id() */
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andi t2, t0, 0x3 /* thread num */
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sll t0, 2 /* offset in cpu array */
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li t3, CKSEG1ADDR(RESET_DATA_PHYS)
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ADDIU t1, t3, BOOT_CPU_READY
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ADDU t1, t0
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li t3, 1
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sw t3, 0(t1)
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bnez t2, 1f /* skip thread programming */
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nop /* for thread id != 0 */
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/*
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* XLR MMU setup only for first thread in core
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*/
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li t0, 0x400
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mfcr t1, t0
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li t2, 6 /* XLR thread mode mask */
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nor t3, t2, zero
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and t2, t1, t2 /* t2 - current thread mode */
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li v0, CKSEG1ADDR(RESET_DATA_PHYS)
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lw v1, BOOT_THREAD_MODE(v0) /* v1 - new thread mode */
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sll v1, 1
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beq v1, t2, 1f /* same as request value */
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nop /* nothing to do */
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and t2, t1, t3 /* mask out old thread mode */
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or t1, t2, v1 /* put in new value */
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mtcr t1, t0 /* update core control */
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1: wait
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b 1b
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nop
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END(nlm_rmiboot_preboot)
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