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https://github.com/edk2-porting/linux-next.git
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0cd61b68c3
Untested, but this should fix up the bulk of the totally mechanical issues, and should make the actual detail fixing easier. Signed-off-by: Linus Torvalds <torvalds@osdl.org>
130 lines
3.2 KiB
C
130 lines
3.2 KiB
C
/* arch/arm/mach-lh7a40x/irq-lpd7a40x.c
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*
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* Copyright (C) 2004 Coastal Environmental Systems
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* Copyright (C) 2004 Logic Product Development
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* version 2 as published by the Free Software Foundation.
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*
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*/
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/interrupt.h>
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#include <linux/ptrace.h>
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#include <asm/hardware.h>
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#include <asm/irq.h>
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#include <asm/mach/irq.h>
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#include <asm/arch/irqs.h>
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#include "common.h"
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static void lh7a40x_ack_cpld_irq (u32 irq)
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{
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/* CPLD doesn't have ack capability */
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}
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static void lh7a40x_mask_cpld_irq (u32 irq)
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{
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switch (irq) {
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case IRQ_LPD7A40X_ETH_INT:
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CPLD_INTERRUPTS = CPLD_INTERRUPTS | 0x4;
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break;
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case IRQ_LPD7A400_TS:
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CPLD_INTERRUPTS = CPLD_INTERRUPTS | 0x8;
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break;
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}
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}
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static void lh7a40x_unmask_cpld_irq (u32 irq)
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{
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switch (irq) {
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case IRQ_LPD7A40X_ETH_INT:
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CPLD_INTERRUPTS = CPLD_INTERRUPTS & ~ 0x4;
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break;
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case IRQ_LPD7A400_TS:
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CPLD_INTERRUPTS = CPLD_INTERRUPTS & ~ 0x8;
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break;
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}
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}
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static struct irq_chip lh7a40x_cpld_chip = {
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.name = "CPLD",
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.ack = lh7a40x_ack_cpld_irq,
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.mask = lh7a40x_mask_cpld_irq,
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.unmask = lh7a40x_unmask_cpld_irq,
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};
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static void lh7a40x_cpld_handler (unsigned int irq, struct irqdesc *desc)
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{
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unsigned int mask = CPLD_INTERRUPTS;
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desc->chip->ack (irq);
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if ((mask & 0x1) == 0) /* WLAN */
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IRQ_DISPATCH (IRQ_LPD7A40X_ETH_INT);
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if ((mask & 0x2) == 0) /* Touch */
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IRQ_DISPATCH (IRQ_LPD7A400_TS);
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desc->chip->unmask (irq); /* Level-triggered need this */
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}
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/* IRQ initialization */
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void __init lh7a40x_init_board_irq (void)
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{
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int irq;
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/* Rev A (v2.8): PF0, PF1, PF2, and PF3 are available IRQs.
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PF7 supports the CPLD.
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Rev B (v3.4): PF0, PF1, and PF2 are available IRQs.
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PF3 supports the CPLD.
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(Some) LPD7A404 prerelease boards report a version
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number of 0x16, but we force an override since the
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hardware is of the newer variety.
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*/
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unsigned char cpld_version = CPLD_REVISION;
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int pinCPLD;
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#if defined CONFIG_MACH_LPD7A404
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cpld_version = 0x34; /* Override, for now */
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#endif
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pinCPLD = (cpld_version == 0x28) ? 7 : 3;
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/* First, configure user controlled GPIOF interrupts */
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GPIO_PFDD &= ~0x0f; /* PF0-3 are inputs */
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GPIO_INTTYPE1 &= ~0x0f; /* PF0-3 are level triggered */
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GPIO_INTTYPE2 &= ~0x0f; /* PF0-3 are active low */
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barrier ();
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GPIO_GPIOFINTEN |= 0x0f; /* Enable PF0, PF1, PF2, and PF3 IRQs */
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/* Then, configure CPLD interrupt */
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CPLD_INTERRUPTS = 0x0c; /* Disable all CPLD interrupts */
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GPIO_PFDD &= ~(1 << pinCPLD); /* Make input */
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GPIO_INTTYPE1 |= (1 << pinCPLD); /* Edge triggered */
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GPIO_INTTYPE2 &= ~(1 << pinCPLD); /* Active low */
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barrier ();
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GPIO_GPIOFINTEN |= (1 << pinCPLD); /* Enable */
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/* Cascade CPLD interrupts */
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for (irq = IRQ_BOARD_START;
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irq < IRQ_BOARD_START + NR_IRQ_BOARD; ++irq) {
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set_irq_chip (irq, &lh7a40x_cpld_chip);
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set_irq_handler (irq, do_edge_IRQ);
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set_irq_flags (irq, IRQF_VALID);
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}
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set_irq_chained_handler ((cpld_version == 0x28)
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? IRQ_CPLD_V28
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: IRQ_CPLD_V34,
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lh7a40x_cpld_handler);
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}
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