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cd030a78f7
Allwinner R40 SoC have a clock controller module in the style of the SoCs beyond sun6i, however, it's more rich and complex. Add support for it. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
70 lines
1.8 KiB
C
70 lines
1.8 KiB
C
/*
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* Copyright 2017 Icenowy Zheng <icenowy@aosc.io>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef _CCU_SUN8I_R40_H_
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#define _CCU_SUN8I_R40_H_
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#include <dt-bindings/clock/sun8i-r40-ccu.h>
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#include <dt-bindings/reset/sun8i-r40-ccu.h>
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#define CLK_OSC_12M 0
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#define CLK_PLL_CPU 1
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#define CLK_PLL_AUDIO_BASE 2
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#define CLK_PLL_AUDIO 3
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#define CLK_PLL_AUDIO_2X 4
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#define CLK_PLL_AUDIO_4X 5
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#define CLK_PLL_AUDIO_8X 6
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#define CLK_PLL_VIDEO0 7
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#define CLK_PLL_VIDEO0_2X 8
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#define CLK_PLL_VE 9
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#define CLK_PLL_DDR0 10
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#define CLK_PLL_PERIPH0 11
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#define CLK_PLL_PERIPH0_SATA 12
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#define CLK_PLL_PERIPH0_2X 13
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#define CLK_PLL_PERIPH1 14
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#define CLK_PLL_PERIPH1_2X 15
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#define CLK_PLL_VIDEO1 16
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#define CLK_PLL_VIDEO1_2X 17
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#define CLK_PLL_SATA 18
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#define CLK_PLL_SATA_OUT 19
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#define CLK_PLL_GPU 20
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#define CLK_PLL_MIPI 21
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#define CLK_PLL_DE 22
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#define CLK_PLL_DDR1 23
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/* The CPU clock is exported */
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#define CLK_AXI 25
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#define CLK_AHB1 26
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#define CLK_APB1 27
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#define CLK_APB2 28
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/* All the bus gates are exported */
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/* The first bunch of module clocks are exported */
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#define CLK_DRAM 132
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/* All the DRAM gates are exported */
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/* Some more module clocks are exported */
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#define CLK_MBUS 155
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/* Another bunch of module clocks are exported */
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#define CLK_NUMBER (CLK_OUTB + 1)
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#endif /* _CCU_SUN8I_R40_H_ */
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