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d2912cb15b
Based on 2 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation # extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 4122 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Enrico Weigelt <info@metux.net> Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190604081206.933168790@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
104 lines
3.0 KiB
Plaintext
104 lines
3.0 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Common Device Tree Source for IGEP COM MODULE
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*
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* Copyright (C) 2014 Javier Martinez Canillas <javier@osg.samsung.com>
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* Copyright (C) 2014 Enric Balletbo i Serra <eballetbo@gmail.com>
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*/
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#include "omap3-igep.dtsi"
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/ {
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leds: gpio_leds {
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compatible = "gpio-leds";
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user0 {
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label = "omap3:red:user0";
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gpios = <&twl_gpio 18 GPIO_ACTIVE_LOW>; /* LEDA */
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default-state = "off";
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};
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user1 {
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label = "omap3:green:user1";
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gpios = <&twl_gpio 19 GPIO_ACTIVE_LOW>; /* LEDB */
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default-state = "off";
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};
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user2 {
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label = "omap3:red:user1";
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gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; /* gpio_16 */
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default-state = "off";
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};
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};
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hsusb2_phy: hsusb2_phy {
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compatible = "usb-nop-xceiv";
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reset-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>; /* gpio_54 */
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#phy-cells = <0>;
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};
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};
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&omap3_pmx_core {
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pinctrl-names = "default";
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pinctrl-0 = <&hsusb2_pins>;
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hsusb2_pins: pinmux_hsusb2_pins {
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pinctrl-single,pins = <
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OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi1_cs3.hsusb2_data2 */
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OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_clk.hsusb2_data7 */
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OMAP3_CORE1_IOPAD(0x21d8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_simo.hsusb2_data4 */
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OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_somi.hsusb2_data5 */
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OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs0.hsusb2_data6 */
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OMAP3_CORE1_IOPAD(0x21de, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs1.hsusb2_data3 */
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>;
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};
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uart2_pins: pinmux_uart2_pins {
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pinctrl-single,pins = <
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OMAP3_CORE1_IOPAD(0x216c, PIN_INPUT | MUX_MODE1) /* mcbsp3_dx.uart2_cts */
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OMAP3_CORE1_IOPAD(0x216e, PIN_OUTPUT | MUX_MODE1) /* mcbsp3_dr.uart2_rts */
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OMAP3_CORE1_IOPAD(0x2170, PIN_OUTPUT | MUX_MODE1) /* mcbsp3_clk.uart2_tx */
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OMAP3_CORE1_IOPAD(0x2172, PIN_INPUT | MUX_MODE1) /* mcbsp3_fsx.uart2_rx */
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>;
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};
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};
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&omap3_pmx_core2 {
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pinctrl-names = "default";
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pinctrl-0 = <&hsusb2_core2_pins>;
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hsusb2_core2_pins: pinmux_hsusb2_core2_pins {
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pinctrl-single,pins = <
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OMAP3630_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */
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OMAP3630_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */
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OMAP3630_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d12.hsusb2_dir */
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OMAP3630_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d13.hsusb2_nxt */
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OMAP3630_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d14.hsusb2_data0 */
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OMAP3630_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d15.hsusb2_data1 */
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>;
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};
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leds_core2_pins: pinmux_leds_core2_pins {
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pinctrl-single,pins = <
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OMAP3630_CORE2_IOPAD(0x25e0, PIN_OUTPUT | MUX_MODE4) /* etk_d2.gpio_16 */
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>;
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};
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};
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&usbhshost {
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port2-mode = "ehci-phy";
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};
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&usbhsehci {
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phys = <0 &hsusb2_phy>;
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};
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&uart2 {
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pinctrl-names = "default";
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pinctrl-0 = <&uart2_pins>;
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};
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&gpmc {
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ranges = <0 0 0x30000000 0x01000000>; /* CS0: 16MB for NAND */
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};
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