2
0
mirror of https://github.com/edk2-porting/linux-next.git synced 2024-12-27 14:43:58 +08:00
linux-next/arch/arm/boot/dts/at91-wb50n.dtsi
Alexandre Belloni bd5d3873de ARM: dts: at91: sama5d3: switch to new sckc bindings
Remove the child nodes of the sckc as they are not necessary anymore.

Also, switch to the new atmel,sama5d3-sckc compatible string to use the
proper startup time for the RC oscillator (500 µs instead of 75).

Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2019-05-21 17:42:09 +02:00

199 lines
3.6 KiB
Plaintext

// SPDX-License-Identifier: GPL-2.0
/*
* at91-wb50n.dtsi - Device Tree include file for wb50n cpu module
*
* Copyright (C) 2018 Laird
*
*/
#include "sama5d31.dtsi"
/ {
model = "Laird Workgroup Bridge 50N - Atmel SAMA5D";
compatible = "laird,wb50n", "atmel,sama5d31", "atmel,sama5d3", "atmel,sama5";
chosen {
bootargs = "ubi.mtd=6 root=ubi0:rootfs rootfstype=ubifs rw";
stdout-path = "serial0:115200n8";
};
memory {
reg = <0x20000000 0x4000000>;
};
};
&pinctrl {
board {
pinctrl_mmc0_cd: mmc0_cd {
atmel,pins = <AT91_PIOC 26 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>; /* PC26 GPIO with pullup deglitch */
};
pinctrl_usba_vbus: usba_vbus {
atmel,pins = <AT91_PIOB 13 AT91_PERIPH_GPIO AT91_PINCTRL_DEGLITCH>; /* PB13 GPIO with deglitch */
};
};
};
&slow_xtal {
clock-frequency = <32768>;
};
&main_xtal {
clock-frequency = <12000000>;
};
&clk32k {
atmel,osc-bypass;
};
&usart1_clk {
atmel,clk-output-range = <0 132000000>;
};
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_cd>;
cd-gpios = <&pioC 26 GPIO_ACTIVE_LOW>;
slot@0 {
reg = <0>;
bus-width = <4>;
};
};
&mmc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3>;
status = "okay";
atheros@0 {
compatible = "atheros,ath6kl";
atheros,board-id = "SD32";
reg = <0>;
bus-width = <4>;
};
};
&macb1 {
phy-mode = "rmii";
};
&dbgu {
dmas = <0>, <0>; /* Do not use DMA for dbgu */
};
/* On BB40 this port is labeled UART1 */
&usart0 {
atmel,use-dma-rx;
atmel,use-dma-tx;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart0 &pinctrl_usart0_rts_cts>;
};
/* On BB40 this port is labeled UART0 */
&usart1 {
atmel,use-dma-rx;
atmel,use-dma-tx;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart1 &pinctrl_usart1_rts_cts>;
dtr-gpios = <&pioD 13 GPIO_ACTIVE_LOW>;
dsr-gpios = <&pioD 11 GPIO_ACTIVE_LOW>;
dcd-gpios = <&pioD 7 GPIO_ACTIVE_LOW>;
rng-gpios = <&pioD 8 GPIO_ACTIVE_LOW>;
};
/* USART3 is direct-connect to the Bluetooth UART on the radio SIP */
&usart3 {
atmel,use-dma-rx;
atmel,use-dma-tx;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart3 &pinctrl_usart3_rts_cts>;
status = "okay";
};
&spi1 {
cs-gpios = <&pioC 25 0>, <0>, <0>, <0>;
};
&ebi {
pinctrl-0 = <&pinctrl_ebi_nand_addr>;
pinctrl-names = "default";
status = "okay";
};
&nand_controller {
status = "okay";
nand: nand@3 {
reg = <0x3 0x0 0x2>;
atmel,rb = <0>;
nand-bus-width = <8>;
nand-ecc-mode = "hw";
nand-ecc-strength = <8>;
nand-ecc-step-size = <512>;
nand-on-flash-bbt;
label = "atmel_nand";
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
at91bootstrap@0 {
label = "at91bs";
reg = <0x0 0x20000>;
};
uboot@20000 {
label = "u-boot";
reg = <0x20000 0x80000>;
};
ubootenv@a0000 {
label = "u-boot-env";
reg = <0xa0000 0x20000>;
};
ubootenv@c0000 {
label = "u-boot-env";
reg = <0xc0000 0x20000>;
};
kernel-a@e0000 {
label = "kernel-a";
reg = <0xe0000 0x500000>;
};
kernel-b@5e0000 {
label = "kernel-b";
reg = <0x5e0000 0x500000>;
};
rootfs-a@ae0000 {
label = "rootfs-a";
reg = <0xae0000 0x3000000>;
};
rootfs-b@3ae0000 {
label = "rootfs-b";
reg = <0x3ae0000 0x3000000>;
};
user@6ae0000 {
label = "user";
reg = <0x6ae0000 0x14e0000>;
};
};
};
};
&usb0 {
atmel,vbus-gpio = <&pioB 13 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usba_vbus>;
};
&usb1 {
num-ports = <3>;
atmel,vbus-gpio = <&pioA 2 GPIO_ACTIVE_LOW>;
atmel,oc-gpio = <&pioA 4 GPIO_ACTIVE_LOW>;
};