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ce973b141d
QE(QUICC Engine) is a new generation communication coprocessor, which can be found on some of the latest Freescale PowerQUICC CPUs(e.g. MPC8360). The UCC(Unified Communications Controller) module of QE can work as gigabit Ethernet device. This patch provides driver for the device. Signed-off-by: Shlomi Gridish <gridish@freescale.com> Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Jeff Garzik <jeff@garzik.org>
218 lines
6.9 KiB
C
218 lines
6.9 KiB
C
/*
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* Copyright (C) Freescale Semicondutor, Inc. 2006. All rights reserved.
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*
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* Author: Shlomi Gridish <gridish@freescale.com>
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*
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* Description:
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* UCC GETH Driver -- PHY handling
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*
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* Changelog:
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* Jun 28, 2006 Li Yang <LeoLi@freescale.com>
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* - Rearrange code and style fixes
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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*/
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#ifndef __UCC_GETH_PHY_H__
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#define __UCC_GETH_PHY_H__
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#define MII_end ((u32)-2)
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#define MII_read ((u32)-1)
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#define MIIMIND_BUSY 0x00000001
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#define MIIMIND_NOTVALID 0x00000004
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#define UGETH_AN_TIMEOUT 2000
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/* 1000BT control (Marvell & BCM54xx at least) */
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#define MII_1000BASETCONTROL 0x09
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#define MII_1000BASETCONTROL_FULLDUPLEXCAP 0x0200
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#define MII_1000BASETCONTROL_HALFDUPLEXCAP 0x0100
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/* Cicada Extended Control Register 1 */
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#define MII_CIS8201_EXT_CON1 0x17
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#define MII_CIS8201_EXTCON1_INIT 0x0000
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/* Cicada Interrupt Mask Register */
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#define MII_CIS8201_IMASK 0x19
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#define MII_CIS8201_IMASK_IEN 0x8000
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#define MII_CIS8201_IMASK_SPEED 0x4000
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#define MII_CIS8201_IMASK_LINK 0x2000
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#define MII_CIS8201_IMASK_DUPLEX 0x1000
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#define MII_CIS8201_IMASK_MASK 0xf000
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/* Cicada Interrupt Status Register */
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#define MII_CIS8201_ISTAT 0x1a
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#define MII_CIS8201_ISTAT_STATUS 0x8000
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#define MII_CIS8201_ISTAT_SPEED 0x4000
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#define MII_CIS8201_ISTAT_LINK 0x2000
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#define MII_CIS8201_ISTAT_DUPLEX 0x1000
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/* Cicada Auxiliary Control/Status Register */
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#define MII_CIS8201_AUX_CONSTAT 0x1c
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#define MII_CIS8201_AUXCONSTAT_INIT 0x0004
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#define MII_CIS8201_AUXCONSTAT_DUPLEX 0x0020
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#define MII_CIS8201_AUXCONSTAT_SPEED 0x0018
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#define MII_CIS8201_AUXCONSTAT_GBIT 0x0010
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#define MII_CIS8201_AUXCONSTAT_100 0x0008
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/* 88E1011 PHY Status Register */
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#define MII_M1011_PHY_SPEC_STATUS 0x11
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#define MII_M1011_PHY_SPEC_STATUS_1000 0x8000
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#define MII_M1011_PHY_SPEC_STATUS_100 0x4000
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#define MII_M1011_PHY_SPEC_STATUS_SPD_MASK 0xc000
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#define MII_M1011_PHY_SPEC_STATUS_FULLDUPLEX 0x2000
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#define MII_M1011_PHY_SPEC_STATUS_RESOLVED 0x0800
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#define MII_M1011_PHY_SPEC_STATUS_LINK 0x0400
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#define MII_M1011_IEVENT 0x13
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#define MII_M1011_IEVENT_CLEAR 0x0000
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#define MII_M1011_IMASK 0x12
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#define MII_M1011_IMASK_INIT 0x6400
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#define MII_M1011_IMASK_CLEAR 0x0000
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#define MII_DM9161_SCR 0x10
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#define MII_DM9161_SCR_INIT 0x0610
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/* DM9161 Specified Configuration and Status Register */
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#define MII_DM9161_SCSR 0x11
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#define MII_DM9161_SCSR_100F 0x8000
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#define MII_DM9161_SCSR_100H 0x4000
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#define MII_DM9161_SCSR_10F 0x2000
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#define MII_DM9161_SCSR_10H 0x1000
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/* DM9161 Interrupt Register */
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#define MII_DM9161_INTR 0x15
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#define MII_DM9161_INTR_PEND 0x8000
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#define MII_DM9161_INTR_DPLX_MASK 0x0800
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#define MII_DM9161_INTR_SPD_MASK 0x0400
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#define MII_DM9161_INTR_LINK_MASK 0x0200
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#define MII_DM9161_INTR_MASK 0x0100
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#define MII_DM9161_INTR_DPLX_CHANGE 0x0010
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#define MII_DM9161_INTR_SPD_CHANGE 0x0008
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#define MII_DM9161_INTR_LINK_CHANGE 0x0004
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#define MII_DM9161_INTR_INIT 0x0000
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#define MII_DM9161_INTR_STOP \
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(MII_DM9161_INTR_DPLX_MASK | MII_DM9161_INTR_SPD_MASK \
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| MII_DM9161_INTR_LINK_MASK | MII_DM9161_INTR_MASK)
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/* DM9161 10BT Configuration/Status */
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#define MII_DM9161_10BTCSR 0x12
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#define MII_DM9161_10BTCSR_INIT 0x7800
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#define MII_BASIC_FEATURES (SUPPORTED_10baseT_Half | \
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SUPPORTED_10baseT_Full | \
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SUPPORTED_100baseT_Half | \
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SUPPORTED_100baseT_Full | \
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SUPPORTED_Autoneg | \
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SUPPORTED_TP | \
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SUPPORTED_MII)
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#define MII_GBIT_FEATURES (MII_BASIC_FEATURES | \
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SUPPORTED_1000baseT_Half | \
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SUPPORTED_1000baseT_Full)
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#define MII_READ_COMMAND 0x00000001
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#define MII_INTERRUPT_DISABLED 0x0
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#define MII_INTERRUPT_ENABLED 0x1
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/* Taken from mii_if_info and sungem_phy.h */
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struct ugeth_mii_info {
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/* Information about the PHY type */
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/* And management functions */
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struct phy_info *phyinfo;
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ucc_mii_mng_t *mii_regs;
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/* forced speed & duplex (no autoneg)
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* partner speed & duplex & pause (autoneg)
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*/
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int speed;
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int duplex;
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int pause;
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/* The most recently read link state */
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int link;
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/* Enabled Interrupts */
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u32 interrupts;
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u32 advertising;
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int autoneg;
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int mii_id;
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/* private data pointer */
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/* For use by PHYs to maintain extra state */
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void *priv;
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/* Provided by host chip */
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struct net_device *dev;
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/* A lock to ensure that only one thing can read/write
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* the MDIO bus at a time */
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spinlock_t mdio_lock;
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/* Provided by ethernet driver */
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int (*mdio_read) (struct net_device * dev, int mii_id, int reg);
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void (*mdio_write) (struct net_device * dev, int mii_id, int reg,
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int val);
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};
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/* struct phy_info: a structure which defines attributes for a PHY
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*
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* id will contain a number which represents the PHY. During
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* startup, the driver will poll the PHY to find out what its
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* UID--as defined by registers 2 and 3--is. The 32-bit result
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* gotten from the PHY will be ANDed with phy_id_mask to
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* discard any bits which may change based on revision numbers
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* unimportant to functionality
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*
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* There are 6 commands which take a ugeth_mii_info structure.
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* Each PHY must declare config_aneg, and read_status.
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*/
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struct phy_info {
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u32 phy_id;
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char *name;
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unsigned int phy_id_mask;
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u32 features;
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/* Called to initialize the PHY */
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int (*init) (struct ugeth_mii_info * mii_info);
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/* Called to suspend the PHY for power */
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int (*suspend) (struct ugeth_mii_info * mii_info);
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/* Reconfigures autonegotiation (or disables it) */
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int (*config_aneg) (struct ugeth_mii_info * mii_info);
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/* Determines the negotiated speed and duplex */
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int (*read_status) (struct ugeth_mii_info * mii_info);
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/* Clears any pending interrupts */
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int (*ack_interrupt) (struct ugeth_mii_info * mii_info);
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/* Enables or disables interrupts */
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int (*config_intr) (struct ugeth_mii_info * mii_info);
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/* Clears up any memory if needed */
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void (*close) (struct ugeth_mii_info * mii_info);
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};
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struct phy_info *get_phy_info(struct ugeth_mii_info *mii_info);
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void write_phy_reg(struct net_device *dev, int mii_id, int regnum, int value);
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int read_phy_reg(struct net_device *dev, int mii_id, int regnum);
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void mii_clear_phy_interrupt(struct ugeth_mii_info *mii_info);
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void mii_configure_phy_interrupt(struct ugeth_mii_info *mii_info,
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u32 interrupts);
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struct dm9161_private {
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struct timer_list timer;
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int resetdone;
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};
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#endif /* __UCC_GETH_PHY_H__ */
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