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https://github.com/edk2-porting/linux-next.git
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646572c77d
This adds basic support for gate-clocks on Rockchip SoCs. There are 16 gates in each register and use the HIWORD_MASK mechanism for changing gate settings. The gate registers form a continuos block which makes the dt node structure a matter of taste, as either all 160 gates can be put into one gate clock spanning all registers or they can be divided into the 10 individual gates containing 16 clocks each. The code supports both approaches. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Mike Turquette <mturquette@linaro.org>
95 lines
2.3 KiB
C
95 lines
2.3 KiB
C
/*
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* Copyright (c) 2013 MundoReader S.L.
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* Author: Heiko Stuebner <heiko@sntech.de>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/clk-provider.h>
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#include <linux/clkdev.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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static DEFINE_SPINLOCK(clk_lock);
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/*
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* Gate clocks
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*/
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static void __init rk2928_gate_clk_init(struct device_node *node,
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void *data)
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{
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struct clk_onecell_data *clk_data;
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const char *clk_parent;
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const char *clk_name;
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void __iomem *reg;
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void __iomem *reg_idx;
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int flags;
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int qty;
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int reg_bit;
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int clkflags = CLK_SET_RATE_PARENT;
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int i;
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qty = of_property_count_strings(node, "clock-output-names");
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if (qty < 0) {
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pr_err("%s: error in clock-output-names %d\n", __func__, qty);
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return;
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}
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if (qty == 0) {
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pr_info("%s: nothing to do\n", __func__);
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return;
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}
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reg = of_iomap(node, 0);
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clk_data = kzalloc(sizeof(struct clk_onecell_data), GFP_KERNEL);
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if (!clk_data)
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return;
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clk_data->clks = kzalloc(qty * sizeof(struct clk *), GFP_KERNEL);
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if (!clk_data->clks) {
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kfree(clk_data);
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return;
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}
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flags = CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE;
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for (i = 0; i < qty; i++) {
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of_property_read_string_index(node, "clock-output-names",
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i, &clk_name);
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/* ignore empty slots */
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if (!strcmp("reserved", clk_name))
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continue;
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clk_parent = of_clk_get_parent_name(node, i);
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/* keep all gates untouched for now */
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clkflags |= CLK_IGNORE_UNUSED;
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reg_idx = reg + (4 * (i / 16));
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reg_bit = (i % 16);
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clk_data->clks[i] = clk_register_gate(NULL, clk_name,
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clk_parent, clkflags,
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reg_idx, reg_bit,
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flags,
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&clk_lock);
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WARN_ON(IS_ERR(clk_data->clks[i]));
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}
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clk_data->clk_num = qty;
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of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
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}
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CLK_OF_DECLARE(rk2928_gate, "rockchip,rk2928-gate-clk", rk2928_gate_clk_init);
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