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e9ab3214a8
1) Registers the platform device for McBSP on dm365. 2) Add platform data to DM365 EVM board file. 3) Set i2c address for audio codec at DM365 EVM board file. Signed-off-by: Miguel Aguilar <miguel.aguilar@ridgerun.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
81 lines
1.9 KiB
C
81 lines
1.9 KiB
C
/*
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* <mach/asp.h> - DaVinci Audio Serial Port support
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*/
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#ifndef __ASM_ARCH_DAVINCI_ASP_H
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#define __ASM_ARCH_DAVINCI_ASP_H
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#include <mach/irqs.h>
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#include <mach/edma.h>
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/* Bases of dm644x and dm355 register banks */
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#define DAVINCI_ASP0_BASE 0x01E02000
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#define DAVINCI_ASP1_BASE 0x01E04000
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/* Bases of dm365 register banks */
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#define DAVINCI_DM365_ASP0_BASE 0x01D02000
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/* Bases of dm646x register banks */
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#define DAVINCI_DM646X_MCASP0_REG_BASE 0x01D01000
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#define DAVINCI_DM646X_MCASP1_REG_BASE 0x01D01800
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/* Bases of da850/da830 McASP0 register banks */
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#define DAVINCI_DA8XX_MCASP0_REG_BASE 0x01D00000
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/* Bases of da830 McASP1 register banks */
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#define DAVINCI_DA830_MCASP1_REG_BASE 0x01D04000
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/* EDMA channels of dm644x and dm355 */
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#define DAVINCI_DMA_ASP0_TX 2
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#define DAVINCI_DMA_ASP0_RX 3
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#define DAVINCI_DMA_ASP1_TX 8
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#define DAVINCI_DMA_ASP1_RX 9
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/* EDMA channels of dm646x */
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#define DAVINCI_DM646X_DMA_MCASP0_AXEVT0 6
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#define DAVINCI_DM646X_DMA_MCASP0_AREVT0 9
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#define DAVINCI_DM646X_DMA_MCASP1_AXEVT1 12
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/* EDMA channels of da850/da830 McASP0 */
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#define DAVINCI_DA8XX_DMA_MCASP0_AREVT 0
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#define DAVINCI_DA8XX_DMA_MCASP0_AXEVT 1
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/* EDMA channels of da830 McASP1 */
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#define DAVINCI_DA830_DMA_MCASP1_AREVT 2
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#define DAVINCI_DA830_DMA_MCASP1_AXEVT 3
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/* Interrupts */
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#define DAVINCI_ASP0_RX_INT IRQ_MBRINT
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#define DAVINCI_ASP0_TX_INT IRQ_MBXINT
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#define DAVINCI_ASP1_RX_INT IRQ_MBRINT
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#define DAVINCI_ASP1_TX_INT IRQ_MBXINT
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struct snd_platform_data {
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u32 tx_dma_offset;
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u32 rx_dma_offset;
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enum dma_event_q eventq_no; /* event queue number */
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unsigned int codec_fmt;
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/* McASP specific fields */
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int tdm_slots;
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u8 op_mode;
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u8 num_serializer;
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u8 *serial_dir;
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u8 version;
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u8 txnumevt;
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u8 rxnumevt;
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};
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enum {
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MCASP_VERSION_1 = 0, /* DM646x */
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MCASP_VERSION_2, /* DA8xx/OMAPL1x */
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};
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#define INACTIVE_MODE 0
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#define TX_MODE 1
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#define RX_MODE 2
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#define DAVINCI_MCASP_IIS_MODE 0
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#define DAVINCI_MCASP_DIT_MODE 1
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#endif /* __ASM_ARCH_DAVINCI_ASP_H */
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