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c15def1cc3
The DB8500 ED (Early Drop) and V1 are only available inside of ST-Ericsson or partners, we have actively replaced and scrapped these prototypes. All Nova products on the open market (such as the Snowball board) are based on V2 and later ASIC variants. So let us focus on supporting the silicon that will be used and delete this to get a clear overview. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
182 lines
4.7 KiB
C
182 lines
4.7 KiB
C
/*
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* Copyright (C) 2008-2009 ST-Ericsson SA
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*
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* Author: Srinidhi KASAGAR <srinidhi.kasagar@stericsson.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2, as
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* published by the Free Software Foundation.
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*
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*/
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#include <linux/types.h>
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#include <linux/init.h>
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#include <linux/device.h>
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#include <linux/amba/bus.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/platform_device.h>
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#include <linux/io.h>
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#include <asm/mach/map.h>
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#include <asm/pmu.h>
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#include <plat/gpio-nomadik.h>
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#include <mach/hardware.h>
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#include <mach/setup.h>
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#include <mach/devices.h>
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#include <mach/usb.h>
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#include "devices-db8500.h"
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#include "ste-dma40-db8500.h"
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/* minimum static i/o mapping required to boot U8500 platforms */
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static struct map_desc u8500_uart_io_desc[] __initdata = {
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__IO_DEV_DESC(U8500_UART0_BASE, SZ_4K),
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__IO_DEV_DESC(U8500_UART2_BASE, SZ_4K),
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};
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static struct map_desc u8500_io_desc[] __initdata = {
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__IO_DEV_DESC(U8500_GIC_CPU_BASE, SZ_4K),
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__IO_DEV_DESC(U8500_GIC_DIST_BASE, SZ_4K),
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__IO_DEV_DESC(U8500_L2CC_BASE, SZ_4K),
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__IO_DEV_DESC(U8500_TWD_BASE, SZ_4K),
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__IO_DEV_DESC(U8500_MTU0_BASE, SZ_4K),
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__IO_DEV_DESC(U8500_SCU_BASE, SZ_4K),
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__IO_DEV_DESC(U8500_BACKUPRAM0_BASE, SZ_8K),
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__IO_DEV_DESC(U8500_CLKRST1_BASE, SZ_4K),
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__IO_DEV_DESC(U8500_CLKRST2_BASE, SZ_4K),
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__IO_DEV_DESC(U8500_CLKRST3_BASE, SZ_4K),
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__IO_DEV_DESC(U8500_CLKRST5_BASE, SZ_4K),
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__IO_DEV_DESC(U8500_CLKRST6_BASE, SZ_4K),
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__IO_DEV_DESC(U8500_PRCMU_BASE, SZ_4K),
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__IO_DEV_DESC(U8500_GPIO0_BASE, SZ_4K),
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__IO_DEV_DESC(U8500_GPIO1_BASE, SZ_4K),
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__IO_DEV_DESC(U8500_GPIO2_BASE, SZ_4K),
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__IO_DEV_DESC(U8500_GPIO3_BASE, SZ_4K),
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__IO_DEV_DESC(U8500_PRCMU_TCDM_BASE, SZ_4K),
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};
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void __init u8500_map_io(void)
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{
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/*
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* Map the UARTs early so that the DEBUG_LL stuff continues to work.
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*/
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iotable_init(u8500_uart_io_desc, ARRAY_SIZE(u8500_uart_io_desc));
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ux500_map_io();
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iotable_init(u8500_io_desc, ARRAY_SIZE(u8500_io_desc));
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_PRCMU_BASE = __io_address(U8500_PRCMU_BASE);
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}
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static struct resource db8500_pmu_resources[] = {
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[0] = {
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.start = IRQ_DB8500_PMU,
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.end = IRQ_DB8500_PMU,
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.flags = IORESOURCE_IRQ,
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},
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};
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/*
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* The PMU IRQ lines of two cores are wired together into a single interrupt.
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* Bounce the interrupt to the other core if it's not ours.
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*/
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static irqreturn_t db8500_pmu_handler(int irq, void *dev, irq_handler_t handler)
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{
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irqreturn_t ret = handler(irq, dev);
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int other = !smp_processor_id();
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if (ret == IRQ_NONE && cpu_online(other))
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irq_set_affinity(irq, cpumask_of(other));
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/*
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* We should be able to get away with the amount of IRQ_NONEs we give,
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* while still having the spurious IRQ detection code kick in if the
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* interrupt really starts hitting spuriously.
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*/
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return ret;
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}
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static struct arm_pmu_platdata db8500_pmu_platdata = {
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.handle_irq = db8500_pmu_handler,
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};
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static struct platform_device db8500_pmu_device = {
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.name = "arm-pmu",
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.id = ARM_PMU_DEVICE_CPU,
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.num_resources = ARRAY_SIZE(db8500_pmu_resources),
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.resource = db8500_pmu_resources,
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.dev.platform_data = &db8500_pmu_platdata,
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};
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static struct platform_device db8500_prcmu_device = {
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.name = "db8500-prcmu",
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};
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static struct platform_device *platform_devs[] __initdata = {
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&u8500_dma40_device,
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&db8500_pmu_device,
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&db8500_prcmu_device,
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};
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static resource_size_t __initdata db8500_gpio_base[] = {
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U8500_GPIOBANK0_BASE,
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U8500_GPIOBANK1_BASE,
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U8500_GPIOBANK2_BASE,
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U8500_GPIOBANK3_BASE,
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U8500_GPIOBANK4_BASE,
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U8500_GPIOBANK5_BASE,
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U8500_GPIOBANK6_BASE,
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U8500_GPIOBANK7_BASE,
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U8500_GPIOBANK8_BASE,
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};
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static void __init db8500_add_gpios(void)
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{
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struct nmk_gpio_platform_data pdata = {
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.supports_sleepmode = true,
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};
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dbx500_add_gpios(ARRAY_AND_SIZE(db8500_gpio_base),
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IRQ_DB8500_GPIO0, &pdata);
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}
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static int usb_db8500_rx_dma_cfg[] = {
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DB8500_DMA_DEV38_USB_OTG_IEP_1_9,
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DB8500_DMA_DEV37_USB_OTG_IEP_2_10,
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DB8500_DMA_DEV36_USB_OTG_IEP_3_11,
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DB8500_DMA_DEV19_USB_OTG_IEP_4_12,
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DB8500_DMA_DEV18_USB_OTG_IEP_5_13,
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DB8500_DMA_DEV17_USB_OTG_IEP_6_14,
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DB8500_DMA_DEV16_USB_OTG_IEP_7_15,
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DB8500_DMA_DEV39_USB_OTG_IEP_8
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};
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static int usb_db8500_tx_dma_cfg[] = {
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DB8500_DMA_DEV38_USB_OTG_OEP_1_9,
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DB8500_DMA_DEV37_USB_OTG_OEP_2_10,
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DB8500_DMA_DEV36_USB_OTG_OEP_3_11,
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DB8500_DMA_DEV19_USB_OTG_OEP_4_12,
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DB8500_DMA_DEV18_USB_OTG_OEP_5_13,
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DB8500_DMA_DEV17_USB_OTG_OEP_6_14,
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DB8500_DMA_DEV16_USB_OTG_OEP_7_15,
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DB8500_DMA_DEV39_USB_OTG_OEP_8
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};
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/*
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* This function is called from the board init
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*/
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void __init u8500_init_devices(void)
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{
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db8500_add_rtc();
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db8500_add_gpios();
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db8500_add_usb(usb_db8500_rx_dma_cfg, usb_db8500_tx_dma_cfg);
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platform_device_register_simple("cpufreq-u8500", -1, NULL, 0);
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platform_add_devices(platform_devs, ARRAY_SIZE(platform_devs));
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return ;
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}
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