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c89eeda810
Not all configurations of the Denali controller support 4 banks. The controller can support between 1 and 16 banks. Detect this from the design features register. Signed-off-by: Jamie Iles <jamie@jamieiles.com> Signed-off-by: Artem Bityutskiy <Artem.Bityutskiy@nokia.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
500 lines
15 KiB
C
500 lines
15 KiB
C
/*
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* NAND Flash Controller Device Driver
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* Copyright (c) 2009 - 2010, Intel Corporation and its suppliers.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
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*
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*/
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#include <linux/mtd/nand.h>
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#define DEVICE_RESET 0x0
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#define DEVICE_RESET__BANK0 0x0001
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#define DEVICE_RESET__BANK1 0x0002
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#define DEVICE_RESET__BANK2 0x0004
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#define DEVICE_RESET__BANK3 0x0008
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#define TRANSFER_SPARE_REG 0x10
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#define TRANSFER_SPARE_REG__FLAG 0x0001
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#define LOAD_WAIT_CNT 0x20
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#define LOAD_WAIT_CNT__VALUE 0xffff
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#define PROGRAM_WAIT_CNT 0x30
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#define PROGRAM_WAIT_CNT__VALUE 0xffff
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#define ERASE_WAIT_CNT 0x40
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#define ERASE_WAIT_CNT__VALUE 0xffff
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#define INT_MON_CYCCNT 0x50
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#define INT_MON_CYCCNT__VALUE 0xffff
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#define RB_PIN_ENABLED 0x60
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#define RB_PIN_ENABLED__BANK0 0x0001
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#define RB_PIN_ENABLED__BANK1 0x0002
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#define RB_PIN_ENABLED__BANK2 0x0004
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#define RB_PIN_ENABLED__BANK3 0x0008
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#define MULTIPLANE_OPERATION 0x70
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#define MULTIPLANE_OPERATION__FLAG 0x0001
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#define MULTIPLANE_READ_ENABLE 0x80
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#define MULTIPLANE_READ_ENABLE__FLAG 0x0001
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#define COPYBACK_DISABLE 0x90
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#define COPYBACK_DISABLE__FLAG 0x0001
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#define CACHE_WRITE_ENABLE 0xa0
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#define CACHE_WRITE_ENABLE__FLAG 0x0001
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#define CACHE_READ_ENABLE 0xb0
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#define CACHE_READ_ENABLE__FLAG 0x0001
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#define PREFETCH_MODE 0xc0
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#define PREFETCH_MODE__PREFETCH_EN 0x0001
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#define PREFETCH_MODE__PREFETCH_BURST_LENGTH 0xfff0
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#define CHIP_ENABLE_DONT_CARE 0xd0
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#define CHIP_EN_DONT_CARE__FLAG 0x01
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#define ECC_ENABLE 0xe0
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#define ECC_ENABLE__FLAG 0x0001
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#define GLOBAL_INT_ENABLE 0xf0
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#define GLOBAL_INT_EN_FLAG 0x01
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#define WE_2_RE 0x100
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#define WE_2_RE__VALUE 0x003f
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#define ADDR_2_DATA 0x110
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#define ADDR_2_DATA__VALUE 0x003f
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#define RE_2_WE 0x120
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#define RE_2_WE__VALUE 0x003f
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#define ACC_CLKS 0x130
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#define ACC_CLKS__VALUE 0x000f
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#define NUMBER_OF_PLANES 0x140
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#define NUMBER_OF_PLANES__VALUE 0x0007
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#define PAGES_PER_BLOCK 0x150
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#define PAGES_PER_BLOCK__VALUE 0xffff
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#define DEVICE_WIDTH 0x160
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#define DEVICE_WIDTH__VALUE 0x0003
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#define DEVICE_MAIN_AREA_SIZE 0x170
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#define DEVICE_MAIN_AREA_SIZE__VALUE 0xffff
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#define DEVICE_SPARE_AREA_SIZE 0x180
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#define DEVICE_SPARE_AREA_SIZE__VALUE 0xffff
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#define TWO_ROW_ADDR_CYCLES 0x190
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#define TWO_ROW_ADDR_CYCLES__FLAG 0x0001
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#define MULTIPLANE_ADDR_RESTRICT 0x1a0
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#define MULTIPLANE_ADDR_RESTRICT__FLAG 0x0001
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#define ECC_CORRECTION 0x1b0
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#define ECC_CORRECTION__VALUE 0x001f
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#define READ_MODE 0x1c0
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#define READ_MODE__VALUE 0x000f
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#define WRITE_MODE 0x1d0
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#define WRITE_MODE__VALUE 0x000f
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#define COPYBACK_MODE 0x1e0
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#define COPYBACK_MODE__VALUE 0x000f
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#define RDWR_EN_LO_CNT 0x1f0
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#define RDWR_EN_LO_CNT__VALUE 0x001f
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#define RDWR_EN_HI_CNT 0x200
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#define RDWR_EN_HI_CNT__VALUE 0x001f
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#define MAX_RD_DELAY 0x210
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#define MAX_RD_DELAY__VALUE 0x000f
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#define CS_SETUP_CNT 0x220
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#define CS_SETUP_CNT__VALUE 0x001f
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#define SPARE_AREA_SKIP_BYTES 0x230
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#define SPARE_AREA_SKIP_BYTES__VALUE 0x003f
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#define SPARE_AREA_MARKER 0x240
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#define SPARE_AREA_MARKER__VALUE 0xffff
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#define DEVICES_CONNECTED 0x250
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#define DEVICES_CONNECTED__VALUE 0x0007
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#define DIE_MASK 0x260
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#define DIE_MASK__VALUE 0x00ff
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#define FIRST_BLOCK_OF_NEXT_PLANE 0x270
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#define FIRST_BLOCK_OF_NEXT_PLANE__VALUE 0xffff
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#define WRITE_PROTECT 0x280
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#define WRITE_PROTECT__FLAG 0x0001
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#define RE_2_RE 0x290
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#define RE_2_RE__VALUE 0x003f
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#define MANUFACTURER_ID 0x300
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#define MANUFACTURER_ID__VALUE 0x00ff
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#define DEVICE_ID 0x310
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#define DEVICE_ID__VALUE 0x00ff
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#define DEVICE_PARAM_0 0x320
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#define DEVICE_PARAM_0__VALUE 0x00ff
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#define DEVICE_PARAM_1 0x330
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#define DEVICE_PARAM_1__VALUE 0x00ff
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#define DEVICE_PARAM_2 0x340
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#define DEVICE_PARAM_2__VALUE 0x00ff
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#define LOGICAL_PAGE_DATA_SIZE 0x350
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#define LOGICAL_PAGE_DATA_SIZE__VALUE 0xffff
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#define LOGICAL_PAGE_SPARE_SIZE 0x360
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#define LOGICAL_PAGE_SPARE_SIZE__VALUE 0xffff
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#define REVISION 0x370
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#define REVISION__VALUE 0xffff
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#define ONFI_DEVICE_FEATURES 0x380
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#define ONFI_DEVICE_FEATURES__VALUE 0x003f
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#define ONFI_OPTIONAL_COMMANDS 0x390
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#define ONFI_OPTIONAL_COMMANDS__VALUE 0x003f
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#define ONFI_TIMING_MODE 0x3a0
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#define ONFI_TIMING_MODE__VALUE 0x003f
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#define ONFI_PGM_CACHE_TIMING_MODE 0x3b0
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#define ONFI_PGM_CACHE_TIMING_MODE__VALUE 0x003f
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#define ONFI_DEVICE_NO_OF_LUNS 0x3c0
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#define ONFI_DEVICE_NO_OF_LUNS__NO_OF_LUNS 0x00ff
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#define ONFI_DEVICE_NO_OF_LUNS__ONFI_DEVICE 0x0100
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#define ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_L 0x3d0
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#define ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_L__VALUE 0xffff
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#define ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_U 0x3e0
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#define ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_U__VALUE 0xffff
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#define FEATURES 0x3f0
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#define FEATURES__N_BANKS 0x0003
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#define FEATURES__ECC_MAX_ERR 0x003c
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#define FEATURES__DMA 0x0040
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#define FEATURES__CMD_DMA 0x0080
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#define FEATURES__PARTITION 0x0100
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#define FEATURES__XDMA_SIDEBAND 0x0200
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#define FEATURES__GPREG 0x0400
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#define FEATURES__INDEX_ADDR 0x0800
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#define TRANSFER_MODE 0x400
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#define TRANSFER_MODE__VALUE 0x0003
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#define INTR_STATUS(__bank) (0x410 + ((__bank) * 0x50))
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#define INTR_EN(__bank) (0x420 + ((__bank) * 0x50))
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#define INTR_STATUS__ECC_TRANSACTION_DONE 0x0001
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#define INTR_STATUS__ECC_ERR 0x0002
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#define INTR_STATUS__DMA_CMD_COMP 0x0004
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#define INTR_STATUS__TIME_OUT 0x0008
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#define INTR_STATUS__PROGRAM_FAIL 0x0010
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#define INTR_STATUS__ERASE_FAIL 0x0020
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#define INTR_STATUS__LOAD_COMP 0x0040
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#define INTR_STATUS__PROGRAM_COMP 0x0080
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#define INTR_STATUS__ERASE_COMP 0x0100
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#define INTR_STATUS__PIPE_CPYBCK_CMD_COMP 0x0200
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#define INTR_STATUS__LOCKED_BLK 0x0400
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#define INTR_STATUS__UNSUP_CMD 0x0800
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#define INTR_STATUS__INT_ACT 0x1000
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#define INTR_STATUS__RST_COMP 0x2000
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#define INTR_STATUS__PIPE_CMD_ERR 0x4000
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#define INTR_STATUS__PAGE_XFER_INC 0x8000
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#define INTR_EN__ECC_TRANSACTION_DONE 0x0001
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#define INTR_EN__ECC_ERR 0x0002
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#define INTR_EN__DMA_CMD_COMP 0x0004
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#define INTR_EN__TIME_OUT 0x0008
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#define INTR_EN__PROGRAM_FAIL 0x0010
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#define INTR_EN__ERASE_FAIL 0x0020
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#define INTR_EN__LOAD_COMP 0x0040
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#define INTR_EN__PROGRAM_COMP 0x0080
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#define INTR_EN__ERASE_COMP 0x0100
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#define INTR_EN__PIPE_CPYBCK_CMD_COMP 0x0200
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#define INTR_EN__LOCKED_BLK 0x0400
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#define INTR_EN__UNSUP_CMD 0x0800
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#define INTR_EN__INT_ACT 0x1000
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#define INTR_EN__RST_COMP 0x2000
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#define INTR_EN__PIPE_CMD_ERR 0x4000
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#define INTR_EN__PAGE_XFER_INC 0x8000
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#define PAGE_CNT(__bank) (0x430 + ((__bank) * 0x50))
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#define ERR_PAGE_ADDR(__bank) (0x440 + ((__bank) * 0x50))
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#define ERR_BLOCK_ADDR(__bank) (0x450 + ((__bank) * 0x50))
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#define DATA_INTR 0x550
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#define DATA_INTR__WRITE_SPACE_AV 0x0001
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#define DATA_INTR__READ_DATA_AV 0x0002
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#define DATA_INTR_EN 0x560
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#define DATA_INTR_EN__WRITE_SPACE_AV 0x0001
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#define DATA_INTR_EN__READ_DATA_AV 0x0002
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#define GPREG_0 0x570
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#define GPREG_0__VALUE 0xffff
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#define GPREG_1 0x580
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#define GPREG_1__VALUE 0xffff
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#define GPREG_2 0x590
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#define GPREG_2__VALUE 0xffff
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#define GPREG_3 0x5a0
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#define GPREG_3__VALUE 0xffff
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#define ECC_THRESHOLD 0x600
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#define ECC_THRESHOLD__VALUE 0x03ff
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#define ECC_ERROR_BLOCK_ADDRESS 0x610
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#define ECC_ERROR_BLOCK_ADDRESS__VALUE 0xffff
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#define ECC_ERROR_PAGE_ADDRESS 0x620
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#define ECC_ERROR_PAGE_ADDRESS__VALUE 0x0fff
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#define ECC_ERROR_PAGE_ADDRESS__BANK 0xf000
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#define ECC_ERROR_ADDRESS 0x630
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#define ECC_ERROR_ADDRESS__OFFSET 0x0fff
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#define ECC_ERROR_ADDRESS__SECTOR_NR 0xf000
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#define ERR_CORRECTION_INFO 0x640
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#define ERR_CORRECTION_INFO__BYTEMASK 0x00ff
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#define ERR_CORRECTION_INFO__DEVICE_NR 0x0f00
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#define ERR_CORRECTION_INFO__ERROR_TYPE 0x4000
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#define ERR_CORRECTION_INFO__LAST_ERR_INFO 0x8000
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#define DMA_ENABLE 0x700
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#define DMA_ENABLE__FLAG 0x0001
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#define IGNORE_ECC_DONE 0x710
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#define IGNORE_ECC_DONE__FLAG 0x0001
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#define DMA_INTR 0x720
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#define DMA_INTR__TARGET_ERROR 0x0001
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#define DMA_INTR__DESC_COMP_CHANNEL0 0x0002
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#define DMA_INTR__DESC_COMP_CHANNEL1 0x0004
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#define DMA_INTR__DESC_COMP_CHANNEL2 0x0008
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#define DMA_INTR__DESC_COMP_CHANNEL3 0x0010
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#define DMA_INTR__MEMCOPY_DESC_COMP 0x0020
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#define DMA_INTR_EN 0x730
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#define DMA_INTR_EN__TARGET_ERROR 0x0001
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#define DMA_INTR_EN__DESC_COMP_CHANNEL0 0x0002
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#define DMA_INTR_EN__DESC_COMP_CHANNEL1 0x0004
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#define DMA_INTR_EN__DESC_COMP_CHANNEL2 0x0008
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#define DMA_INTR_EN__DESC_COMP_CHANNEL3 0x0010
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#define DMA_INTR_EN__MEMCOPY_DESC_COMP 0x0020
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#define TARGET_ERR_ADDR_LO 0x740
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#define TARGET_ERR_ADDR_LO__VALUE 0xffff
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#define TARGET_ERR_ADDR_HI 0x750
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#define TARGET_ERR_ADDR_HI__VALUE 0xffff
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#define CHNL_ACTIVE 0x760
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#define CHNL_ACTIVE__CHANNEL0 0x0001
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#define CHNL_ACTIVE__CHANNEL1 0x0002
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#define CHNL_ACTIVE__CHANNEL2 0x0004
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#define CHNL_ACTIVE__CHANNEL3 0x0008
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#define ACTIVE_SRC_ID 0x800
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#define ACTIVE_SRC_ID__VALUE 0x00ff
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#define PTN_INTR 0x810
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#define PTN_INTR__CONFIG_ERROR 0x0001
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#define PTN_INTR__ACCESS_ERROR_BANK0 0x0002
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#define PTN_INTR__ACCESS_ERROR_BANK1 0x0004
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#define PTN_INTR__ACCESS_ERROR_BANK2 0x0008
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#define PTN_INTR__ACCESS_ERROR_BANK3 0x0010
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#define PTN_INTR__REG_ACCESS_ERROR 0x0020
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#define PTN_INTR_EN 0x820
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#define PTN_INTR_EN__CONFIG_ERROR 0x0001
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#define PTN_INTR_EN__ACCESS_ERROR_BANK0 0x0002
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#define PTN_INTR_EN__ACCESS_ERROR_BANK1 0x0004
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#define PTN_INTR_EN__ACCESS_ERROR_BANK2 0x0008
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#define PTN_INTR_EN__ACCESS_ERROR_BANK3 0x0010
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#define PTN_INTR_EN__REG_ACCESS_ERROR 0x0020
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#define PERM_SRC_ID(__bank) (0x830 + ((__bank) * 0x40))
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#define PERM_SRC_ID__SRCID 0x00ff
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#define PERM_SRC_ID__DIRECT_ACCESS_ACTIVE 0x0800
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#define PERM_SRC_ID__WRITE_ACTIVE 0x2000
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#define PERM_SRC_ID__READ_ACTIVE 0x4000
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#define PERM_SRC_ID__PARTITION_VALID 0x8000
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#define MIN_BLK_ADDR(__bank) (0x840 + ((__bank) * 0x40))
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#define MIN_BLK_ADDR__VALUE 0xffff
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#define MAX_BLK_ADDR(__bank) (0x850 + ((__bank) * 0x40))
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#define MAX_BLK_ADDR__VALUE 0xffff
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#define MIN_MAX_BANK(__bank) (0x860 + ((__bank) * 0x40))
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#define MIN_MAX_BANK__MIN_VALUE 0x0003
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#define MIN_MAX_BANK__MAX_VALUE 0x000c
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/* ffsdefs.h */
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#define CLEAR 0 /*use this to clear a field instead of "fail"*/
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#define SET 1 /*use this to set a field instead of "pass"*/
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#define FAIL 1 /*failed flag*/
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#define PASS 0 /*success flag*/
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#define ERR -1 /*error flag*/
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/* lld.h */
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#define GOOD_BLOCK 0
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#define DEFECTIVE_BLOCK 1
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#define READ_ERROR 2
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#define CLK_X 5
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#define CLK_MULTI 4
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/* spectraswconfig.h */
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#define CMD_DMA 0
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#define SPECTRA_PARTITION_ID 0
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/**** Block Table and Reserved Block Parameters *****/
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#define SPECTRA_START_BLOCK 3
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#define NUM_FREE_BLOCKS_GATE 30
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/* KBV - Updated to LNW scratch register address */
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#define SCRATCH_REG_ADDR CONFIG_MTD_NAND_DENALI_SCRATCH_REG_ADDR
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#define SCRATCH_REG_SIZE 64
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#define GLOB_HWCTL_DEFAULT_BLKS 2048
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#define SUPPORT_15BITECC 1
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#define SUPPORT_8BITECC 1
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#define CUSTOM_CONF_PARAMS 0
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#define ONFI_BLOOM_TIME 1
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#define MODE5_WORKAROUND 0
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/* lld_nand.h */
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/*
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* NAND Flash Controller Device Driver
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* Copyright (c) 2009, Intel Corporation and its suppliers.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
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*
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*/
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#ifndef _LLD_NAND_
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#define _LLD_NAND_
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#define MODE_00 0x00000000
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#define MODE_01 0x04000000
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#define MODE_10 0x08000000
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#define MODE_11 0x0C000000
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#define DATA_TRANSFER_MODE 0
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#define PROTECTION_PER_BLOCK 1
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#define LOAD_WAIT_COUNT 2
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#define PROGRAM_WAIT_COUNT 3
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#define ERASE_WAIT_COUNT 4
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#define INT_MONITOR_CYCLE_COUNT 5
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#define READ_BUSY_PIN_ENABLED 6
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#define MULTIPLANE_OPERATION_SUPPORT 7
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#define PRE_FETCH_MODE 8
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#define CE_DONT_CARE_SUPPORT 9
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#define COPYBACK_SUPPORT 10
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#define CACHE_WRITE_SUPPORT 11
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#define CACHE_READ_SUPPORT 12
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#define NUM_PAGES_IN_BLOCK 13
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#define ECC_ENABLE_SELECT 14
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#define WRITE_ENABLE_2_READ_ENABLE 15
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#define ADDRESS_2_DATA 16
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#define READ_ENABLE_2_WRITE_ENABLE 17
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#define TWO_ROW_ADDRESS_CYCLES 18
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#define MULTIPLANE_ADDRESS_RESTRICT 19
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#define ACC_CLOCKS 20
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#define READ_WRITE_ENABLE_LOW_COUNT 21
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#define READ_WRITE_ENABLE_HIGH_COUNT 22
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#define ECC_SECTOR_SIZE 512
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#define DENALI_BUF_SIZE (NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE)
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struct nand_buf {
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int head;
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int tail;
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uint8_t buf[DENALI_BUF_SIZE];
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dma_addr_t dma_buf;
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};
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#define INTEL_CE4100 1
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#define INTEL_MRST 2
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struct denali_nand_info {
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struct mtd_info mtd;
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struct nand_chip nand;
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int flash_bank; /* currently selected chip */
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int status;
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int platform;
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struct nand_buf buf;
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struct device *dev;
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int total_used_banks;
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uint32_t block; /* stored for future use */
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uint16_t page;
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void __iomem *flash_reg; /* Mapped io reg base address */
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void __iomem *flash_mem; /* Mapped io reg base address */
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/* elements used by ISR */
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struct completion complete;
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spinlock_t irq_lock;
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uint32_t irq_status;
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int irq_debug_array[32];
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int idx;
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uint32_t devnum; /* represent how many nands connected */
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uint32_t fwblks; /* represent how many blocks FW used */
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uint32_t totalblks;
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uint32_t blksperchip;
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uint32_t bbtskipbytes;
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uint32_t max_banks;
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};
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#endif /*_LLD_NAND_*/
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