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5328666939
irq_domain_mapping is a rather useful tool to understand how IRqs are mapped in irqdomains, and yet it is not documented anywhere. Let's address this. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Link: http://lkml.kernel.org/r/20170512115538.10767-5-marc.zyngier@arm.com Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
273 lines
13 KiB
Plaintext
273 lines
13 KiB
Plaintext
irq_domain interrupt number mapping library
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The current design of the Linux kernel uses a single large number
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space where each separate IRQ source is assigned a different number.
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This is simple when there is only one interrupt controller, but in
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systems with multiple interrupt controllers the kernel must ensure
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that each one gets assigned non-overlapping allocations of Linux
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IRQ numbers.
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The number of interrupt controllers registered as unique irqchips
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show a rising tendency: for example subdrivers of different kinds
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such as GPIO controllers avoid reimplementing identical callback
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mechanisms as the IRQ core system by modelling their interrupt
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handlers as irqchips, i.e. in effect cascading interrupt controllers.
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Here the interrupt number loose all kind of correspondence to
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hardware interrupt numbers: whereas in the past, IRQ numbers could
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be chosen so they matched the hardware IRQ line into the root
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interrupt controller (i.e. the component actually fireing the
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interrupt line to the CPU) nowadays this number is just a number.
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For this reason we need a mechanism to separate controller-local
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interrupt numbers, called hardware irq's, from Linux IRQ numbers.
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The irq_alloc_desc*() and irq_free_desc*() APIs provide allocation of
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irq numbers, but they don't provide any support for reverse mapping of
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the controller-local IRQ (hwirq) number into the Linux IRQ number
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space.
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The irq_domain library adds mapping between hwirq and IRQ numbers on
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top of the irq_alloc_desc*() API. An irq_domain to manage mapping is
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preferred over interrupt controller drivers open coding their own
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reverse mapping scheme.
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irq_domain also implements translation from an abstract irq_fwspec
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structure to hwirq numbers (Device Tree and ACPI GSI so far), and can
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be easily extended to support other IRQ topology data sources.
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=== irq_domain usage ===
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An interrupt controller driver creates and registers an irq_domain by
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calling one of the irq_domain_add_*() functions (each mapping method
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has a different allocator function, more on that later). The function
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will return a pointer to the irq_domain on success. The caller must
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provide the allocator function with an irq_domain_ops structure.
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In most cases, the irq_domain will begin empty without any mappings
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between hwirq and IRQ numbers. Mappings are added to the irq_domain
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by calling irq_create_mapping() which accepts the irq_domain and a
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hwirq number as arguments. If a mapping for the hwirq doesn't already
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exist then it will allocate a new Linux irq_desc, associate it with
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the hwirq, and call the .map() callback so the driver can perform any
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required hardware setup.
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When an interrupt is received, irq_find_mapping() function should
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be used to find the Linux IRQ number from the hwirq number.
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The irq_create_mapping() function must be called *atleast once*
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before any call to irq_find_mapping(), lest the descriptor will not
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be allocated.
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If the driver has the Linux IRQ number or the irq_data pointer, and
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needs to know the associated hwirq number (such as in the irq_chip
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callbacks) then it can be directly obtained from irq_data->hwirq.
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=== Types of irq_domain mappings ===
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There are several mechanisms available for reverse mapping from hwirq
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to Linux irq, and each mechanism uses a different allocation function.
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Which reverse map type should be used depends on the use case. Each
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of the reverse map types are described below:
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==== Linear ====
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irq_domain_add_linear()
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irq_domain_create_linear()
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The linear reverse map maintains a fixed size table indexed by the
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hwirq number. When a hwirq is mapped, an irq_desc is allocated for
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the hwirq, and the IRQ number is stored in the table.
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The Linear map is a good choice when the maximum number of hwirqs is
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fixed and a relatively small number (~ < 256). The advantages of this
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map are fixed time lookup for IRQ numbers, and irq_descs are only
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allocated for in-use IRQs. The disadvantage is that the table must be
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as large as the largest possible hwirq number.
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irq_domain_add_linear() and irq_domain_create_linear() are functionally
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equivalent, except for the first argument is different - the former
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accepts an Open Firmware specific 'struct device_node', while the latter
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accepts a more general abstraction 'struct fwnode_handle'.
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The majority of drivers should use the linear map.
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==== Tree ====
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irq_domain_add_tree()
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irq_domain_create_tree()
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The irq_domain maintains a radix tree map from hwirq numbers to Linux
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IRQs. When an hwirq is mapped, an irq_desc is allocated and the
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hwirq is used as the lookup key for the radix tree.
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The tree map is a good choice if the hwirq number can be very large
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since it doesn't need to allocate a table as large as the largest
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hwirq number. The disadvantage is that hwirq to IRQ number lookup is
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dependent on how many entries are in the table.
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irq_domain_add_tree() and irq_domain_create_tree() are functionally
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equivalent, except for the first argument is different - the former
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accepts an Open Firmware specific 'struct device_node', while the latter
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accepts a more general abstraction 'struct fwnode_handle'.
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Very few drivers should need this mapping.
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==== No Map ===-
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irq_domain_add_nomap()
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The No Map mapping is to be used when the hwirq number is
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programmable in the hardware. In this case it is best to program the
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Linux IRQ number into the hardware itself so that no mapping is
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required. Calling irq_create_direct_mapping() will allocate a Linux
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IRQ number and call the .map() callback so that driver can program the
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Linux IRQ number into the hardware.
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Most drivers cannot use this mapping.
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==== Legacy ====
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irq_domain_add_simple()
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irq_domain_add_legacy()
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irq_domain_add_legacy_isa()
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The Legacy mapping is a special case for drivers that already have a
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range of irq_descs allocated for the hwirqs. It is used when the
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driver cannot be immediately converted to use the linear mapping. For
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example, many embedded system board support files use a set of #defines
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for IRQ numbers that are passed to struct device registrations. In that
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case the Linux IRQ numbers cannot be dynamically assigned and the legacy
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mapping should be used.
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The legacy map assumes a contiguous range of IRQ numbers has already
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been allocated for the controller and that the IRQ number can be
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calculated by adding a fixed offset to the hwirq number, and
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visa-versa. The disadvantage is that it requires the interrupt
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controller to manage IRQ allocations and it requires an irq_desc to be
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allocated for every hwirq, even if it is unused.
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The legacy map should only be used if fixed IRQ mappings must be
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supported. For example, ISA controllers would use the legacy map for
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mapping Linux IRQs 0-15 so that existing ISA drivers get the correct IRQ
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numbers.
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Most users of legacy mappings should use irq_domain_add_simple() which
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will use a legacy domain only if an IRQ range is supplied by the
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system and will otherwise use a linear domain mapping. The semantics
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of this call are such that if an IRQ range is specified then
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descriptors will be allocated on-the-fly for it, and if no range is
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specified it will fall through to irq_domain_add_linear() which means
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*no* irq descriptors will be allocated.
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A typical use case for simple domains is where an irqchip provider
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is supporting both dynamic and static IRQ assignments.
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In order to avoid ending up in a situation where a linear domain is
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used and no descriptor gets allocated it is very important to make sure
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that the driver using the simple domain call irq_create_mapping()
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before any irq_find_mapping() since the latter will actually work
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for the static IRQ assignment case.
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==== Hierarchy IRQ domain ====
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On some architectures, there may be multiple interrupt controllers
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involved in delivering an interrupt from the device to the target CPU.
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Let's look at a typical interrupt delivering path on x86 platforms:
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Device --> IOAPIC -> Interrupt remapping Controller -> Local APIC -> CPU
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There are three interrupt controllers involved:
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1) IOAPIC controller
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2) Interrupt remapping controller
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3) Local APIC controller
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To support such a hardware topology and make software architecture match
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hardware architecture, an irq_domain data structure is built for each
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interrupt controller and those irq_domains are organized into hierarchy.
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When building irq_domain hierarchy, the irq_domain near to the device is
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child and the irq_domain near to CPU is parent. So a hierarchy structure
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as below will be built for the example above.
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CPU Vector irq_domain (root irq_domain to manage CPU vectors)
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^
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Interrupt Remapping irq_domain (manage irq_remapping entries)
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^
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IOAPIC irq_domain (manage IOAPIC delivery entries/pins)
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There are four major interfaces to use hierarchy irq_domain:
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1) irq_domain_alloc_irqs(): allocate IRQ descriptors and interrupt
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controller related resources to deliver these interrupts.
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2) irq_domain_free_irqs(): free IRQ descriptors and interrupt controller
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related resources associated with these interrupts.
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3) irq_domain_activate_irq(): activate interrupt controller hardware to
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deliver the interrupt.
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4) irq_domain_deactivate_irq(): deactivate interrupt controller hardware
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to stop delivering the interrupt.
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Following changes are needed to support hierarchy irq_domain.
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1) a new field 'parent' is added to struct irq_domain; it's used to
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maintain irq_domain hierarchy information.
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2) a new field 'parent_data' is added to struct irq_data; it's used to
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build hierarchy irq_data to match hierarchy irq_domains. The irq_data
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is used to store irq_domain pointer and hardware irq number.
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3) new callbacks are added to struct irq_domain_ops to support hierarchy
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irq_domain operations.
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With support of hierarchy irq_domain and hierarchy irq_data ready, an
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irq_domain structure is built for each interrupt controller, and an
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irq_data structure is allocated for each irq_domain associated with an
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IRQ. Now we could go one step further to support stacked(hierarchy)
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irq_chip. That is, an irq_chip is associated with each irq_data along
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the hierarchy. A child irq_chip may implement a required action by
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itself or by cooperating with its parent irq_chip.
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With stacked irq_chip, interrupt controller driver only needs to deal
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with the hardware managed by itself and may ask for services from its
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parent irq_chip when needed. So we could achieve a much cleaner
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software architecture.
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For an interrupt controller driver to support hierarchy irq_domain, it
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needs to:
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1) Implement irq_domain_ops.alloc and irq_domain_ops.free
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2) Optionally implement irq_domain_ops.activate and
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irq_domain_ops.deactivate.
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3) Optionally implement an irq_chip to manage the interrupt controller
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hardware.
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4) No need to implement irq_domain_ops.map and irq_domain_ops.unmap,
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they are unused with hierarchy irq_domain.
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Hierarchy irq_domain is in no way x86 specific, and is heavily used to
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support other architectures, such as ARM, ARM64 etc.
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=== Debugging ===
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If you switch on CONFIG_IRQ_DOMAIN_DEBUG (which depends on
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CONFIG_IRQ_DOMAIN and CONFIG_DEBUG_FS), you will find a new file in
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your debugfs mount point, called irq_domain_mapping. This file
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contains a live snapshot of all the IRQ domains in the system:
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name mapped linear-max direct-max devtree-node
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pl061 8 8 0 /smb/gpio@e0080000
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pl061 8 8 0 /smb/gpio@e1050000
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pMSI 0 0 0 /interrupt-controller@e1101000/v2m@e0080000
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MSI 37 0 0 /interrupt-controller@e1101000/v2m@e0080000
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GICv2m 37 0 0 /interrupt-controller@e1101000/v2m@e0080000
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GICv2 448 448 0 /interrupt-controller@e1101000
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it also iterates over the interrupts to display their mapping in the
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domains, and makes the domain stacking visible:
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irq hwirq chip name chip data active type domain
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1 0x00019 GICv2 0xffff00000916bfd8 * LINEAR GICv2
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2 0x0001d GICv2 0xffff00000916bfd8 LINEAR GICv2
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3 0x0001e GICv2 0xffff00000916bfd8 * LINEAR GICv2
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4 0x0001b GICv2 0xffff00000916bfd8 * LINEAR GICv2
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5 0x0001a GICv2 0xffff00000916bfd8 LINEAR GICv2
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[...]
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96 0x81808 MSI 0x (null) RADIX MSI
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96+ 0x00063 GICv2m 0xffff8003ee116980 RADIX GICv2m
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96+ 0x00063 GICv2 0xffff00000916bfd8 LINEAR GICv2
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97 0x08800 MSI 0x (null) * RADIX MSI
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97+ 0x00064 GICv2m 0xffff8003ee116980 * RADIX GICv2m
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97+ 0x00064 GICv2 0xffff00000916bfd8 * LINEAR GICv2
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Here, interrupts 1-5 are only using a single domain, while 96 and 97
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are build out of a stack of three domain, each level performing a
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particular function.
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