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72aa0d899a
Use i915_gem_object_pin_map() for the guc client's lifetime to replace
the peristent kmap + frequent kmap_atomic with a permanent vmapping.
This avoids taking the obj->mm.lock mutex whilst inside irq context
later.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=98571
Fixes: 96d7763452 ("drm/i915: Use a radixtree for random access...");
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: http://patchwork.freedesktop.org/patch/msgid/20161102175051.29163-9-chris@chris-wilson.co.uk
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
194 lines
6.7 KiB
C
194 lines
6.7 KiB
C
/*
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* Copyright © 2014 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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*/
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#ifndef _INTEL_GUC_H_
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#define _INTEL_GUC_H_
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#include "intel_guc_fwif.h"
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#include "i915_guc_reg.h"
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#include "intel_ringbuffer.h"
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struct drm_i915_gem_request;
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/*
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* This structure primarily describes the GEM object shared with the GuC.
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* The GEM object is held for the entire lifetime of our interaction with
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* the GuC, being allocated before the GuC is loaded with its firmware.
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* Because there's no way to update the address used by the GuC after
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* initialisation, the shared object must stay pinned into the GGTT as
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* long as the GuC is in use. We also keep the first page (only) mapped
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* into kernel address space, as it includes shared data that must be
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* updated on every request submission.
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*
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* The single GEM object described here is actually made up of several
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* separate areas, as far as the GuC is concerned. The first page (kept
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* kmap'd) includes the "process decriptor" which holds sequence data for
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* the doorbell, and one cacheline which actually *is* the doorbell; a
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* write to this will "ring the doorbell" (i.e. send an interrupt to the
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* GuC). The subsequent pages of the client object constitute the work
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* queue (a circular array of work items), again described in the process
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* descriptor. Work queue pages are mapped momentarily as required.
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*
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* We also keep a few statistics on failures. Ideally, these should all
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* be zero!
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* no_wq_space: times that the submission pre-check found no space was
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* available in the work queue (note, the queue is shared,
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* not per-engine). It is OK for this to be nonzero, but
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* it should not be huge!
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* q_fail: failed to enqueue a work item. This should never happen,
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* because we check for space beforehand.
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* b_fail: failed to ring the doorbell. This should never happen, unless
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* somehow the hardware misbehaves, or maybe if the GuC firmware
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* crashes? We probably need to reset the GPU to recover.
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* retcode: errno from last guc_submit()
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*/
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struct i915_guc_client {
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struct i915_vma *vma;
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void *vaddr;
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struct i915_gem_context *owner;
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struct intel_guc *guc;
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uint32_t engines; /* bitmap of (host) engine ids */
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uint32_t priority;
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uint32_t ctx_index;
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uint32_t proc_desc_offset;
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uint32_t doorbell_offset;
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uint32_t cookie;
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uint16_t doorbell_id;
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uint16_t padding[3]; /* Maintain alignment */
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spinlock_t wq_lock;
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uint32_t wq_offset;
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uint32_t wq_size;
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uint32_t wq_tail;
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uint32_t wq_rsvd;
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uint32_t no_wq_space;
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uint32_t b_fail;
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int retcode;
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/* Per-engine counts of GuC submissions */
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uint64_t submissions[I915_NUM_ENGINES];
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};
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enum intel_guc_fw_status {
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GUC_FIRMWARE_FAIL = -1,
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GUC_FIRMWARE_NONE = 0,
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GUC_FIRMWARE_PENDING,
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GUC_FIRMWARE_SUCCESS
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};
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/*
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* This structure encapsulates all the data needed during the process
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* of fetching, caching, and loading the firmware image into the GuC.
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*/
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struct intel_guc_fw {
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struct drm_device * guc_dev;
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const char * guc_fw_path;
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size_t guc_fw_size;
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struct drm_i915_gem_object * guc_fw_obj;
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enum intel_guc_fw_status guc_fw_fetch_status;
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enum intel_guc_fw_status guc_fw_load_status;
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uint16_t guc_fw_major_wanted;
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uint16_t guc_fw_minor_wanted;
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uint16_t guc_fw_major_found;
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uint16_t guc_fw_minor_found;
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uint32_t header_size;
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uint32_t header_offset;
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uint32_t rsa_size;
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uint32_t rsa_offset;
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uint32_t ucode_size;
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uint32_t ucode_offset;
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};
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struct intel_guc_log {
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uint32_t flags;
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struct i915_vma *vma;
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void *buf_addr;
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struct workqueue_struct *flush_wq;
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struct work_struct flush_work;
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struct rchan *relay_chan;
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/* logging related stats */
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u32 capture_miss_count;
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u32 flush_interrupt_count;
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u32 prev_overflow_count[GUC_MAX_LOG_BUFFER];
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u32 total_overflow_count[GUC_MAX_LOG_BUFFER];
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u32 flush_count[GUC_MAX_LOG_BUFFER];
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};
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struct intel_guc {
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struct intel_guc_fw guc_fw;
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struct intel_guc_log log;
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/* GuC2Host interrupt related state */
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bool interrupts_enabled;
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struct i915_vma *ads_vma;
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struct i915_vma *ctx_pool_vma;
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struct ida ctx_ids;
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struct i915_guc_client *execbuf_client;
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DECLARE_BITMAP(doorbell_bitmap, GUC_MAX_DOORBELLS);
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uint32_t db_cacheline; /* Cyclic counter mod pagesize */
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/* Action status & statistics */
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uint64_t action_count; /* Total commands issued */
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uint32_t action_cmd; /* Last command word */
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uint32_t action_status; /* Last return status */
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uint32_t action_fail; /* Total number of failures */
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int32_t action_err; /* Last error code */
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uint64_t submissions[I915_NUM_ENGINES];
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uint32_t last_seqno[I915_NUM_ENGINES];
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/* To serialize the Host2GuC actions */
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struct mutex action_lock;
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};
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/* intel_guc_loader.c */
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extern void intel_guc_init(struct drm_device *dev);
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extern int intel_guc_setup(struct drm_device *dev);
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extern void intel_guc_fini(struct drm_device *dev);
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extern const char *intel_guc_fw_status_repr(enum intel_guc_fw_status status);
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extern int intel_guc_suspend(struct drm_device *dev);
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extern int intel_guc_resume(struct drm_device *dev);
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/* i915_guc_submission.c */
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int i915_guc_submission_init(struct drm_i915_private *dev_priv);
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int i915_guc_submission_enable(struct drm_i915_private *dev_priv);
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int i915_guc_wq_reserve(struct drm_i915_gem_request *rq);
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void i915_guc_wq_unreserve(struct drm_i915_gem_request *request);
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void i915_guc_submission_disable(struct drm_i915_private *dev_priv);
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void i915_guc_submission_fini(struct drm_i915_private *dev_priv);
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void i915_guc_capture_logs(struct drm_i915_private *dev_priv);
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void i915_guc_flush_logs(struct drm_i915_private *dev_priv);
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void i915_guc_register(struct drm_i915_private *dev_priv);
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void i915_guc_unregister(struct drm_i915_private *dev_priv);
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int i915_guc_log_control(struct drm_i915_private *dev_priv, u64 control_val);
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#endif
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