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94c12cc7d1
Major cleanup of all s390 inline assemblies. They now have a common coding style. Quite a few have been shortened, mainly by using register asm variables. Use of the EX_TABLE macro helps as well. The atomic ops, bit ops and locking inlines new use the Q-constraint if a newer gcc is used. That results in slightly better code. Thanks to Christian Borntraeger for proof reading the changes. Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
266 lines
6.9 KiB
C
266 lines
6.9 KiB
C
#ifndef __ARCH_S390_ATOMIC__
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#define __ARCH_S390_ATOMIC__
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#include <linux/compiler.h>
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/*
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* include/asm-s390/atomic.h
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*
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* S390 version
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* Copyright (C) 1999-2005 IBM Deutschland Entwicklung GmbH, IBM Corporation
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* Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com),
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* Denis Joseph Barrow,
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* Arnd Bergmann (arndb@de.ibm.com)
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*
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* Derived from "include/asm-i386/bitops.h"
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* Copyright (C) 1992, Linus Torvalds
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*
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*/
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/*
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* Atomic operations that C can't guarantee us. Useful for
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* resource counting etc..
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* S390 uses 'Compare And Swap' for atomicity in SMP enviroment
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*/
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typedef struct {
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volatile int counter;
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} __attribute__ ((aligned (4))) atomic_t;
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#define ATOMIC_INIT(i) { (i) }
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#ifdef __KERNEL__
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#if __GNUC__ > 3 || (__GNUC__ == 3 && __GNUC_MINOR__ > 2)
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#define __CS_LOOP(ptr, op_val, op_string) ({ \
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typeof(ptr->counter) old_val, new_val; \
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asm volatile( \
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" l %0,%2\n" \
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"0: lr %1,%0\n" \
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op_string " %1,%3\n" \
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" cs %0,%1,%2\n" \
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" jl 0b" \
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: "=&d" (old_val), "=&d" (new_val), \
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"=Q" (((atomic_t *)(ptr))->counter) \
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: "d" (op_val), "Q" (((atomic_t *)(ptr))->counter) \
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: "cc", "memory"); \
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new_val; \
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})
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#else /* __GNUC__ */
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#define __CS_LOOP(ptr, op_val, op_string) ({ \
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typeof(ptr->counter) old_val, new_val; \
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asm volatile( \
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" l %0,0(%3)\n" \
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"0: lr %1,%0\n" \
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op_string " %1,%4\n" \
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" cs %0,%1,0(%3)\n" \
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" jl 0b" \
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: "=&d" (old_val), "=&d" (new_val), \
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"=m" (((atomic_t *)(ptr))->counter) \
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: "a" (ptr), "d" (op_val), \
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"m" (((atomic_t *)(ptr))->counter) \
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: "cc", "memory"); \
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new_val; \
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})
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#endif /* __GNUC__ */
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#define atomic_read(v) ((v)->counter)
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#define atomic_set(v,i) (((v)->counter) = (i))
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static __inline__ int atomic_add_return(int i, atomic_t * v)
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{
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return __CS_LOOP(v, i, "ar");
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}
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#define atomic_add(_i, _v) atomic_add_return(_i, _v)
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#define atomic_add_negative(_i, _v) (atomic_add_return(_i, _v) < 0)
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#define atomic_inc(_v) atomic_add_return(1, _v)
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#define atomic_inc_return(_v) atomic_add_return(1, _v)
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#define atomic_inc_and_test(_v) (atomic_add_return(1, _v) == 0)
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static __inline__ int atomic_sub_return(int i, atomic_t * v)
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{
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return __CS_LOOP(v, i, "sr");
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}
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#define atomic_sub(_i, _v) atomic_sub_return(_i, _v)
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#define atomic_sub_and_test(_i, _v) (atomic_sub_return(_i, _v) == 0)
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#define atomic_dec(_v) atomic_sub_return(1, _v)
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#define atomic_dec_return(_v) atomic_sub_return(1, _v)
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#define atomic_dec_and_test(_v) (atomic_sub_return(1, _v) == 0)
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static __inline__ void atomic_clear_mask(unsigned long mask, atomic_t * v)
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{
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__CS_LOOP(v, ~mask, "nr");
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}
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static __inline__ void atomic_set_mask(unsigned long mask, atomic_t * v)
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{
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__CS_LOOP(v, mask, "or");
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}
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#define atomic_xchg(v, new) (xchg(&((v)->counter), new))
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static __inline__ int atomic_cmpxchg(atomic_t *v, int old, int new)
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{
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#if __GNUC__ > 3 || (__GNUC__ == 3 && __GNUC_MINOR__ > 2)
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asm volatile(
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" cs %0,%2,%1"
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: "+d" (old), "=Q" (v->counter)
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: "d" (new), "Q" (v->counter)
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: "cc", "memory");
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#else /* __GNUC__ */
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asm volatile(
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" cs %0,%3,0(%2)"
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: "+d" (old), "=m" (v->counter)
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: "a" (v), "d" (new), "m" (v->counter)
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: "cc", "memory");
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#endif /* __GNUC__ */
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return old;
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}
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static __inline__ int atomic_add_unless(atomic_t *v, int a, int u)
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{
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int c, old;
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c = atomic_read(v);
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for (;;) {
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if (unlikely(c == u))
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break;
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old = atomic_cmpxchg(v, c, c + a);
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if (likely(old == c))
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break;
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c = old;
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}
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return c != u;
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}
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#define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0)
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#undef __CS_LOOP
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#ifdef __s390x__
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typedef struct {
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volatile long long counter;
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} __attribute__ ((aligned (8))) atomic64_t;
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#define ATOMIC64_INIT(i) { (i) }
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#if __GNUC__ > 3 || (__GNUC__ == 3 && __GNUC_MINOR__ > 2)
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#define __CSG_LOOP(ptr, op_val, op_string) ({ \
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typeof(ptr->counter) old_val, new_val; \
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asm volatile( \
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" lg %0,%2\n" \
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"0: lgr %1,%0\n" \
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op_string " %1,%3\n" \
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" csg %0,%1,%2\n" \
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" jl 0b" \
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: "=&d" (old_val), "=&d" (new_val), \
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"=Q" (((atomic_t *)(ptr))->counter) \
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: "d" (op_val), "Q" (((atomic_t *)(ptr))->counter) \
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: "cc", "memory" ); \
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new_val; \
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})
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#else /* __GNUC__ */
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#define __CSG_LOOP(ptr, op_val, op_string) ({ \
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typeof(ptr->counter) old_val, new_val; \
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asm volatile( \
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" lg %0,0(%3)\n" \
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"0: lgr %1,%0\n" \
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op_string " %1,%4\n" \
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" csg %0,%1,0(%3)\n" \
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" jl 0b" \
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: "=&d" (old_val), "=&d" (new_val), \
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"=m" (((atomic_t *)(ptr))->counter) \
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: "a" (ptr), "d" (op_val), \
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"m" (((atomic_t *)(ptr))->counter) \
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: "cc", "memory" ); \
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new_val; \
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})
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#endif /* __GNUC__ */
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#define atomic64_read(v) ((v)->counter)
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#define atomic64_set(v,i) (((v)->counter) = (i))
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static __inline__ long long atomic64_add_return(long long i, atomic64_t * v)
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{
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return __CSG_LOOP(v, i, "agr");
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}
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#define atomic64_add(_i, _v) atomic64_add_return(_i, _v)
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#define atomic64_add_negative(_i, _v) (atomic64_add_return(_i, _v) < 0)
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#define atomic64_inc(_v) atomic64_add_return(1, _v)
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#define atomic64_inc_return(_v) atomic64_add_return(1, _v)
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#define atomic64_inc_and_test(_v) (atomic64_add_return(1, _v) == 0)
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static __inline__ long long atomic64_sub_return(long long i, atomic64_t * v)
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{
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return __CSG_LOOP(v, i, "sgr");
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}
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#define atomic64_sub(_i, _v) atomic64_sub_return(_i, _v)
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#define atomic64_sub_and_test(_i, _v) (atomic64_sub_return(_i, _v) == 0)
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#define atomic64_dec(_v) atomic64_sub_return(1, _v)
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#define atomic64_dec_return(_v) atomic64_sub_return(1, _v)
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#define atomic64_dec_and_test(_v) (atomic64_sub_return(1, _v) == 0)
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static __inline__ void atomic64_clear_mask(unsigned long mask, atomic64_t * v)
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{
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__CSG_LOOP(v, ~mask, "ngr");
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}
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static __inline__ void atomic64_set_mask(unsigned long mask, atomic64_t * v)
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{
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__CSG_LOOP(v, mask, "ogr");
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}
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static __inline__ long long atomic64_cmpxchg(atomic64_t *v,
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long long old, long long new)
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{
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#if __GNUC__ > 3 || (__GNUC__ == 3 && __GNUC_MINOR__ > 2)
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asm volatile(
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" csg %0,%2,%1"
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: "+d" (old), "=Q" (v->counter)
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: "d" (new), "Q" (v->counter)
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: "cc", "memory");
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#else /* __GNUC__ */
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asm volatile(
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" csg %0,%3,0(%2)"
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: "+d" (old), "=m" (v->counter)
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: "a" (v), "d" (new), "m" (v->counter)
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: "cc", "memory");
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#endif /* __GNUC__ */
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return old;
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}
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static __inline__ int atomic64_add_unless(atomic64_t *v,
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long long a, long long u)
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{
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long long c, old;
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c = atomic64_read(v);
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for (;;) {
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if (unlikely(c == u))
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break;
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old = atomic64_cmpxchg(v, c, c + a);
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if (likely(old == c))
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break;
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c = old;
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}
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return c != u;
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}
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#define atomic64_inc_not_zero(v) atomic64_add_unless((v), 1, 0)
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#undef __CSG_LOOP
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#endif
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#define smp_mb__before_atomic_dec() smp_mb()
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#define smp_mb__after_atomic_dec() smp_mb()
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#define smp_mb__before_atomic_inc() smp_mb()
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#define smp_mb__after_atomic_inc() smp_mb()
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#include <asm-generic/atomic.h>
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#endif /* __KERNEL__ */
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#endif /* __ARCH_S390_ATOMIC__ */
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