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00b65985fb
Instead of pinning per-cpu TLB into a DTR, use DTC. This will free up one TLB entry for application, or even kernel if access pattern to per-cpu data area has high temporal locality. Since per-cpu is mapped at the top of region 7 address, we just need to add special case in alt_dtlb_miss. The physical address of per-cpu data is already conveniently stored in IA64_KR(PER_CPU_DATA). Latency for alt_dtlb_miss is not affected as we can hide all the latency. It was measured that alt_dtlb_miss handler has 23 cycles latency before and after the patch. The performance effect is massive for applications that put lots of tlb pressure on CPU. Workload environment like database online transaction processing or application uses tera-byte of memory would benefit the most. Measurement with industry standard database benchmark shown an upward of 1.6% gain. While smaller workloads like cpu, java also showing small improvement. Signed-off-by: Ken Chen <kenneth.w.chen@intel.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
163 lines
6.6 KiB
C
163 lines
6.6 KiB
C
#ifndef _ASM_IA64_KREGS_H
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#define _ASM_IA64_KREGS_H
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/*
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* Copyright (C) 2001-2002 Hewlett-Packard Co
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* David Mosberger-Tang <davidm@hpl.hp.com>
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*/
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/*
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* This file defines the kernel register usage convention used by Linux/ia64.
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*/
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/*
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* Kernel registers:
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*/
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#define IA64_KR_IO_BASE 0 /* ar.k0: legacy I/O base address */
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#define IA64_KR_TSSD 1 /* ar.k1: IVE uses this as the TSSD */
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#define IA64_KR_PER_CPU_DATA 3 /* ar.k3: physical per-CPU base */
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#define IA64_KR_CURRENT_STACK 4 /* ar.k4: what's mapped in IA64_TR_CURRENT_STACK */
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#define IA64_KR_FPU_OWNER 5 /* ar.k5: fpu-owner (UP only, at the moment) */
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#define IA64_KR_CURRENT 6 /* ar.k6: "current" task pointer */
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#define IA64_KR_PT_BASE 7 /* ar.k7: page table base address (physical) */
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#define _IA64_KR_PASTE(x,y) x##y
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#define _IA64_KR_PREFIX(n) _IA64_KR_PASTE(ar.k, n)
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#define IA64_KR(n) _IA64_KR_PREFIX(IA64_KR_##n)
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/*
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* Translation registers:
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*/
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#define IA64_TR_KERNEL 0 /* itr0, dtr0: maps kernel image (code & data) */
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#define IA64_TR_PALCODE 1 /* itr1: maps PALcode as required by EFI */
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#define IA64_TR_CURRENT_STACK 1 /* dtr1: maps kernel's memory- & register-stacks */
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/* Processor status register bits: */
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#define IA64_PSR_BE_BIT 1
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#define IA64_PSR_UP_BIT 2
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#define IA64_PSR_AC_BIT 3
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#define IA64_PSR_MFL_BIT 4
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#define IA64_PSR_MFH_BIT 5
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#define IA64_PSR_IC_BIT 13
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#define IA64_PSR_I_BIT 14
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#define IA64_PSR_PK_BIT 15
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#define IA64_PSR_DT_BIT 17
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#define IA64_PSR_DFL_BIT 18
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#define IA64_PSR_DFH_BIT 19
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#define IA64_PSR_SP_BIT 20
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#define IA64_PSR_PP_BIT 21
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#define IA64_PSR_DI_BIT 22
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#define IA64_PSR_SI_BIT 23
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#define IA64_PSR_DB_BIT 24
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#define IA64_PSR_LP_BIT 25
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#define IA64_PSR_TB_BIT 26
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#define IA64_PSR_RT_BIT 27
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/* The following are not affected by save_flags()/restore_flags(): */
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#define IA64_PSR_CPL0_BIT 32
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#define IA64_PSR_CPL1_BIT 33
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#define IA64_PSR_IS_BIT 34
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#define IA64_PSR_MC_BIT 35
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#define IA64_PSR_IT_BIT 36
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#define IA64_PSR_ID_BIT 37
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#define IA64_PSR_DA_BIT 38
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#define IA64_PSR_DD_BIT 39
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#define IA64_PSR_SS_BIT 40
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#define IA64_PSR_RI_BIT 41
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#define IA64_PSR_ED_BIT 43
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#define IA64_PSR_BN_BIT 44
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#define IA64_PSR_IA_BIT 45
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/* A mask of PSR bits that we generally don't want to inherit across a clone2() or an
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execve(). Only list flags here that need to be cleared/set for BOTH clone2() and
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execve(). */
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#define IA64_PSR_BITS_TO_CLEAR (IA64_PSR_MFL | IA64_PSR_MFH | IA64_PSR_DB | IA64_PSR_LP | \
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IA64_PSR_TB | IA64_PSR_ID | IA64_PSR_DA | IA64_PSR_DD | \
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IA64_PSR_SS | IA64_PSR_ED | IA64_PSR_IA)
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#define IA64_PSR_BITS_TO_SET (IA64_PSR_DFH | IA64_PSR_SP)
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#define IA64_PSR_BE (__IA64_UL(1) << IA64_PSR_BE_BIT)
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#define IA64_PSR_UP (__IA64_UL(1) << IA64_PSR_UP_BIT)
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#define IA64_PSR_AC (__IA64_UL(1) << IA64_PSR_AC_BIT)
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#define IA64_PSR_MFL (__IA64_UL(1) << IA64_PSR_MFL_BIT)
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#define IA64_PSR_MFH (__IA64_UL(1) << IA64_PSR_MFH_BIT)
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#define IA64_PSR_IC (__IA64_UL(1) << IA64_PSR_IC_BIT)
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#define IA64_PSR_I (__IA64_UL(1) << IA64_PSR_I_BIT)
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#define IA64_PSR_PK (__IA64_UL(1) << IA64_PSR_PK_BIT)
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#define IA64_PSR_DT (__IA64_UL(1) << IA64_PSR_DT_BIT)
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#define IA64_PSR_DFL (__IA64_UL(1) << IA64_PSR_DFL_BIT)
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#define IA64_PSR_DFH (__IA64_UL(1) << IA64_PSR_DFH_BIT)
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#define IA64_PSR_SP (__IA64_UL(1) << IA64_PSR_SP_BIT)
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#define IA64_PSR_PP (__IA64_UL(1) << IA64_PSR_PP_BIT)
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#define IA64_PSR_DI (__IA64_UL(1) << IA64_PSR_DI_BIT)
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#define IA64_PSR_SI (__IA64_UL(1) << IA64_PSR_SI_BIT)
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#define IA64_PSR_DB (__IA64_UL(1) << IA64_PSR_DB_BIT)
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#define IA64_PSR_LP (__IA64_UL(1) << IA64_PSR_LP_BIT)
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#define IA64_PSR_TB (__IA64_UL(1) << IA64_PSR_TB_BIT)
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#define IA64_PSR_RT (__IA64_UL(1) << IA64_PSR_RT_BIT)
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/* The following are not affected by save_flags()/restore_flags(): */
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#define IA64_PSR_CPL (__IA64_UL(3) << IA64_PSR_CPL0_BIT)
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#define IA64_PSR_IS (__IA64_UL(1) << IA64_PSR_IS_BIT)
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#define IA64_PSR_MC (__IA64_UL(1) << IA64_PSR_MC_BIT)
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#define IA64_PSR_IT (__IA64_UL(1) << IA64_PSR_IT_BIT)
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#define IA64_PSR_ID (__IA64_UL(1) << IA64_PSR_ID_BIT)
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#define IA64_PSR_DA (__IA64_UL(1) << IA64_PSR_DA_BIT)
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#define IA64_PSR_DD (__IA64_UL(1) << IA64_PSR_DD_BIT)
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#define IA64_PSR_SS (__IA64_UL(1) << IA64_PSR_SS_BIT)
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#define IA64_PSR_RI (__IA64_UL(3) << IA64_PSR_RI_BIT)
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#define IA64_PSR_ED (__IA64_UL(1) << IA64_PSR_ED_BIT)
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#define IA64_PSR_BN (__IA64_UL(1) << IA64_PSR_BN_BIT)
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#define IA64_PSR_IA (__IA64_UL(1) << IA64_PSR_IA_BIT)
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/* User mask bits: */
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#define IA64_PSR_UM (IA64_PSR_BE | IA64_PSR_UP | IA64_PSR_AC | IA64_PSR_MFL | IA64_PSR_MFH)
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/* Default Control Register */
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#define IA64_DCR_PP_BIT 0 /* privileged performance monitor default */
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#define IA64_DCR_BE_BIT 1 /* big-endian default */
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#define IA64_DCR_LC_BIT 2 /* ia32 lock-check enable */
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#define IA64_DCR_DM_BIT 8 /* defer TLB miss faults */
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#define IA64_DCR_DP_BIT 9 /* defer page-not-present faults */
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#define IA64_DCR_DK_BIT 10 /* defer key miss faults */
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#define IA64_DCR_DX_BIT 11 /* defer key permission faults */
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#define IA64_DCR_DR_BIT 12 /* defer access right faults */
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#define IA64_DCR_DA_BIT 13 /* defer access bit faults */
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#define IA64_DCR_DD_BIT 14 /* defer debug faults */
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#define IA64_DCR_PP (__IA64_UL(1) << IA64_DCR_PP_BIT)
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#define IA64_DCR_BE (__IA64_UL(1) << IA64_DCR_BE_BIT)
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#define IA64_DCR_LC (__IA64_UL(1) << IA64_DCR_LC_BIT)
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#define IA64_DCR_DM (__IA64_UL(1) << IA64_DCR_DM_BIT)
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#define IA64_DCR_DP (__IA64_UL(1) << IA64_DCR_DP_BIT)
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#define IA64_DCR_DK (__IA64_UL(1) << IA64_DCR_DK_BIT)
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#define IA64_DCR_DX (__IA64_UL(1) << IA64_DCR_DX_BIT)
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#define IA64_DCR_DR (__IA64_UL(1) << IA64_DCR_DR_BIT)
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#define IA64_DCR_DA (__IA64_UL(1) << IA64_DCR_DA_BIT)
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#define IA64_DCR_DD (__IA64_UL(1) << IA64_DCR_DD_BIT)
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/* Interrupt Status Register */
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#define IA64_ISR_X_BIT 32 /* execute access */
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#define IA64_ISR_W_BIT 33 /* write access */
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#define IA64_ISR_R_BIT 34 /* read access */
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#define IA64_ISR_NA_BIT 35 /* non-access */
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#define IA64_ISR_SP_BIT 36 /* speculative load exception */
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#define IA64_ISR_RS_BIT 37 /* mandatory register-stack exception */
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#define IA64_ISR_IR_BIT 38 /* invalid register frame exception */
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#define IA64_ISR_CODE_MASK 0xf
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#define IA64_ISR_X (__IA64_UL(1) << IA64_ISR_X_BIT)
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#define IA64_ISR_W (__IA64_UL(1) << IA64_ISR_W_BIT)
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#define IA64_ISR_R (__IA64_UL(1) << IA64_ISR_R_BIT)
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#define IA64_ISR_NA (__IA64_UL(1) << IA64_ISR_NA_BIT)
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#define IA64_ISR_SP (__IA64_UL(1) << IA64_ISR_SP_BIT)
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#define IA64_ISR_RS (__IA64_UL(1) << IA64_ISR_RS_BIT)
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#define IA64_ISR_IR (__IA64_UL(1) << IA64_ISR_IR_BIT)
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/* ISR code field for non-access instructions */
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#define IA64_ISR_CODE_TPA 0
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#define IA64_ISR_CODE_FC 1
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#define IA64_ISR_CODE_PROBE 2
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#define IA64_ISR_CODE_TAK 3
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#define IA64_ISR_CODE_LFETCH 4
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#define IA64_ISR_CODE_PROBEF 5
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#endif /* _ASM_IA64_kREGS_H */
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