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4f506daf0e
We get lots of link errors based on the assumption that any s3c24xx kernel would enable CONFIG_PM_SLEEP if it enables CONFIG_PM. This tries to clean that up. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Kukjin Kim <kgene@kernel.org>
137 lines
3.5 KiB
C
137 lines
3.5 KiB
C
/* linux/arch/arm/plat-s3c24xx/pm.c
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*
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* Copyright (c) 2004-2006 Simtec Electronics
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* Ben Dooks <ben@simtec.co.uk>
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*
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* S3C24XX Power Manager (Suspend-To-RAM) support
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*
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* See Documentation/arm/Samsung-S3C24XX/Suspend.txt for more information
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*
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* Parts based on arch/arm/mach-pxa/pm.c
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*
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* Thanks to Dimitry Andric for debugging
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*/
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#include <linux/init.h>
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#include <linux/suspend.h>
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#include <linux/errno.h>
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#include <linux/time.h>
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#include <linux/gpio.h>
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#include <linux/interrupt.h>
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#include <linux/serial_core.h>
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#include <linux/serial_s3c.h>
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#include <linux/io.h>
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#include <mach/regs-clock.h>
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#include <mach/regs-gpio.h>
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#include <mach/regs-irq.h>
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#include <mach/gpio-samsung.h>
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#include <asm/mach/time.h>
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#include <plat/gpio-cfg.h>
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#include <plat/pm.h>
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#include "regs-mem.h"
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#define PFX "s3c24xx-pm: "
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#ifdef CONFIG_PM_SLEEP
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static struct sleep_save core_save[] = {
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/* we restore the timings here, with the proviso that the board
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* brings the system up in an slower, or equal frequency setting
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* to the original system.
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*
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* if we cannot guarantee this, then things are going to go very
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* wrong here, as we modify the refresh and both pll settings.
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*/
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SAVE_ITEM(S3C2410_BWSCON),
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SAVE_ITEM(S3C2410_BANKCON0),
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SAVE_ITEM(S3C2410_BANKCON1),
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SAVE_ITEM(S3C2410_BANKCON2),
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SAVE_ITEM(S3C2410_BANKCON3),
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SAVE_ITEM(S3C2410_BANKCON4),
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SAVE_ITEM(S3C2410_BANKCON5),
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};
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#endif
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/* s3c_pm_check_resume_pin
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*
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* check to see if the pin is configured correctly for sleep mode, and
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* make any necessary adjustments if it is not
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*/
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static void s3c_pm_check_resume_pin(unsigned int pin, unsigned int irqoffs)
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{
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unsigned long irqstate;
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unsigned long pinstate;
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int irq = gpio_to_irq(pin);
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if (irqoffs < 4)
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irqstate = s3c_irqwake_intmask & (1L<<irqoffs);
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else
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irqstate = s3c_irqwake_eintmask & (1L<<irqoffs);
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pinstate = s3c_gpio_getcfg(pin);
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if (!irqstate) {
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if (pinstate == S3C2410_GPIO_IRQ)
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S3C_PMDBG("Leaving IRQ %d (pin %d) as is\n", irq, pin);
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} else {
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if (pinstate == S3C2410_GPIO_IRQ) {
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S3C_PMDBG("Disabling IRQ %d (pin %d)\n", irq, pin);
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s3c_gpio_cfgpin(pin, S3C2410_GPIO_INPUT);
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}
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}
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}
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/* s3c_pm_configure_extint
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*
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* configure all external interrupt pins
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*/
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void s3c_pm_configure_extint(void)
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{
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int pin;
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/* for each of the external interrupts (EINT0..EINT15) we
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* need to check whether it is an external interrupt source,
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* and then configure it as an input if it is not
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*/
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for (pin = S3C2410_GPF(0); pin <= S3C2410_GPF(7); pin++) {
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s3c_pm_check_resume_pin(pin, pin - S3C2410_GPF(0));
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}
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for (pin = S3C2410_GPG(0); pin <= S3C2410_GPG(7); pin++) {
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s3c_pm_check_resume_pin(pin, (pin - S3C2410_GPG(0))+8);
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}
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}
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#ifdef CONFIG_PM_SLEEP
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void s3c_pm_restore_core(void)
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{
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s3c_pm_do_restore_core(core_save, ARRAY_SIZE(core_save));
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}
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void s3c_pm_save_core(void)
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{
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s3c_pm_do_save(core_save, ARRAY_SIZE(core_save));
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}
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#endif
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