David Daney bd6d85c21a MIPS: For Cavium OCTEON handle hazards as per the R10000 handling. ... For Cavium CPU, we treat the same as R10000, in that all hazards are dealt with in hardware. Signed-off-by: Tomaso Paoletti <tpaoletti@caviumnetworks.com> Signed-off-by: Paul Gortmaker <Paul.Gortmaker@windriver.com> Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>		2009-01-11 09:57:21 +00:00
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asm	MIPS: For Cavium OCTEON handle hazards as per the R10000 handling.	2009-01-11 09:57:21 +00:00