mirror of
https://github.com/edk2-porting/linux-next.git
synced 2024-12-24 21:24:00 +08:00
fa4b42b2a9
Updated code with already prepared dev_err_probe(). It reduces code size and simplifies EPROBE_DEFER handling. Also, unify message format for similar error cases. Signed-off-by: Piyush Mehta <piyush.mehta@xilinx.com> Acked-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/20210305091029.23378-1-piyush.mehta@xilinx.com Signed-off-by: Jens Axboe <axboe@kernel.dk>
384 lines
10 KiB
C
384 lines
10 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2015 Xilinx, Inc.
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* CEVA AHCI SATA platform driver
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*
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* based on the AHCI SATA platform driver by Jeff Garzik and Anton Vorontsov
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*/
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#include <linux/ahci_platform.h>
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#include <linux/kernel.h>
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#include <linux/libata.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/reset.h>
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#include "ahci.h"
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/* Vendor Specific Register Offsets */
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#define AHCI_VEND_PCFG 0xA4
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#define AHCI_VEND_PPCFG 0xA8
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#define AHCI_VEND_PP2C 0xAC
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#define AHCI_VEND_PP3C 0xB0
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#define AHCI_VEND_PP4C 0xB4
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#define AHCI_VEND_PP5C 0xB8
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#define AHCI_VEND_AXICC 0xBC
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#define AHCI_VEND_PAXIC 0xC0
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#define AHCI_VEND_PTC 0xC8
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/* Vendor Specific Register bit definitions */
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#define PAXIC_ADBW_BW64 0x1
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#define PAXIC_MAWID(i) (((i) * 2) << 4)
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#define PAXIC_MARID(i) (((i) * 2) << 12)
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#define PAXIC_MARIDD(i) ((((i) * 2) + 1) << 16)
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#define PAXIC_MAWIDD(i) ((((i) * 2) + 1) << 8)
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#define PAXIC_OTL (0x4 << 20)
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/* Register bit definitions for cache control */
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#define AXICC_ARCA_VAL (0xF << 0)
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#define AXICC_ARCF_VAL (0xF << 4)
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#define AXICC_ARCH_VAL (0xF << 8)
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#define AXICC_ARCP_VAL (0xF << 12)
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#define AXICC_AWCFD_VAL (0xF << 16)
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#define AXICC_AWCD_VAL (0xF << 20)
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#define AXICC_AWCF_VAL (0xF << 24)
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#define PCFG_TPSS_VAL (0x32 << 16)
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#define PCFG_TPRS_VAL (0x2 << 12)
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#define PCFG_PAD_VAL 0x2
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#define PPCFG_TTA 0x1FFFE
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#define PPCFG_PSSO_EN (1 << 28)
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#define PPCFG_PSS_EN (1 << 29)
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#define PPCFG_ESDF_EN (1 << 31)
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#define PP5C_RIT 0x60216
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#define PP5C_RCT (0x7f0 << 20)
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#define PTC_RX_WM_VAL 0x40
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#define PTC_RSVD (1 << 27)
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#define PORT0_BASE 0x100
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#define PORT1_BASE 0x180
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/* Port Control Register Bit Definitions */
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#define PORT_SCTL_SPD_GEN3 (0x3 << 4)
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#define PORT_SCTL_SPD_GEN2 (0x2 << 4)
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#define PORT_SCTL_SPD_GEN1 (0x1 << 4)
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#define PORT_SCTL_IPM (0x3 << 8)
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#define PORT_BASE 0x100
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#define PORT_OFFSET 0x80
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#define NR_PORTS 2
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#define DRV_NAME "ahci-ceva"
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#define CEVA_FLAG_BROKEN_GEN2 1
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static unsigned int rx_watermark = PTC_RX_WM_VAL;
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module_param(rx_watermark, uint, 0644);
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MODULE_PARM_DESC(rx_watermark, "RxWaterMark value (0 - 0x80)");
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struct ceva_ahci_priv {
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struct platform_device *ahci_pdev;
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/* Port Phy2Cfg Register */
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u32 pp2c[NR_PORTS];
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u32 pp3c[NR_PORTS];
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u32 pp4c[NR_PORTS];
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u32 pp5c[NR_PORTS];
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/* Axi Cache Control Register */
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u32 axicc;
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bool is_cci_enabled;
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int flags;
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struct reset_control *rst;
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};
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static unsigned int ceva_ahci_read_id(struct ata_device *dev,
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struct ata_taskfile *tf, u16 *id)
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{
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u32 err_mask;
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err_mask = ata_do_dev_read_id(dev, tf, id);
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if (err_mask)
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return err_mask;
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/*
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* Since CEVA controller does not support device sleep feature, we
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* need to clear DEVSLP (bit 8) in word78 of the IDENTIFY DEVICE data.
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*/
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id[ATA_ID_FEATURE_SUPP] &= cpu_to_le16(~(1 << 8));
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return 0;
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}
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static struct ata_port_operations ahci_ceva_ops = {
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.inherits = &ahci_platform_ops,
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.read_id = ceva_ahci_read_id,
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};
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static const struct ata_port_info ahci_ceva_port_info = {
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.flags = AHCI_FLAG_COMMON,
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.pio_mask = ATA_PIO4,
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.udma_mask = ATA_UDMA6,
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.port_ops = &ahci_ceva_ops,
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};
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static void ahci_ceva_setup(struct ahci_host_priv *hpriv)
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{
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void __iomem *mmio = hpriv->mmio;
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struct ceva_ahci_priv *cevapriv = hpriv->plat_data;
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u32 tmp;
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int i;
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/* Set AHCI Enable */
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tmp = readl(mmio + HOST_CTL);
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tmp |= HOST_AHCI_EN;
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writel(tmp, mmio + HOST_CTL);
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for (i = 0; i < NR_PORTS; i++) {
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/* TPSS TPRS scalars, CISE and Port Addr */
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tmp = PCFG_TPSS_VAL | PCFG_TPRS_VAL | (PCFG_PAD_VAL + i);
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writel(tmp, mmio + AHCI_VEND_PCFG);
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/*
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* AXI Data bus width to 64
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* Set Mem Addr Read, Write ID for data transfers
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* Set Mem Addr Read ID, Write ID for non-data transfers
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* Transfer limit to 72 DWord
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*/
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tmp = PAXIC_ADBW_BW64 | PAXIC_MAWIDD(i) | PAXIC_MARIDD(i) |
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PAXIC_MAWID(i) | PAXIC_MARID(i) | PAXIC_OTL;
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writel(tmp, mmio + AHCI_VEND_PAXIC);
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/* Set AXI cache control register if CCi is enabled */
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if (cevapriv->is_cci_enabled) {
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tmp = readl(mmio + AHCI_VEND_AXICC);
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tmp |= AXICC_ARCA_VAL | AXICC_ARCF_VAL |
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AXICC_ARCH_VAL | AXICC_ARCP_VAL |
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AXICC_AWCFD_VAL | AXICC_AWCD_VAL |
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AXICC_AWCF_VAL;
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writel(tmp, mmio + AHCI_VEND_AXICC);
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}
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/* Port Phy Cfg register enables */
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tmp = PPCFG_TTA | PPCFG_PSS_EN | PPCFG_ESDF_EN;
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writel(tmp, mmio + AHCI_VEND_PPCFG);
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/* Phy Control OOB timing parameters COMINIT */
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writel(cevapriv->pp2c[i], mmio + AHCI_VEND_PP2C);
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/* Phy Control OOB timing parameters COMWAKE */
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writel(cevapriv->pp3c[i], mmio + AHCI_VEND_PP3C);
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/* Phy Control Burst timing setting */
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writel(cevapriv->pp4c[i], mmio + AHCI_VEND_PP4C);
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/* Rate Change Timer and Retry Interval Timer setting */
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writel(cevapriv->pp5c[i], mmio + AHCI_VEND_PP5C);
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/* Rx Watermark setting */
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tmp = rx_watermark | PTC_RSVD;
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writel(tmp, mmio + AHCI_VEND_PTC);
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/* Default to Gen 3 Speed and Gen 1 if Gen2 is broken */
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tmp = PORT_SCTL_SPD_GEN3 | PORT_SCTL_IPM;
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if (cevapriv->flags & CEVA_FLAG_BROKEN_GEN2)
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tmp = PORT_SCTL_SPD_GEN1 | PORT_SCTL_IPM;
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writel(tmp, mmio + PORT_SCR_CTL + PORT_BASE + PORT_OFFSET * i);
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}
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}
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static struct scsi_host_template ahci_platform_sht = {
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AHCI_SHT(DRV_NAME),
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};
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static int ceva_ahci_probe(struct platform_device *pdev)
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{
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struct device_node *np = pdev->dev.of_node;
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struct device *dev = &pdev->dev;
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struct ahci_host_priv *hpriv;
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struct ceva_ahci_priv *cevapriv;
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enum dev_dma_attr attr;
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int rc;
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cevapriv = devm_kzalloc(dev, sizeof(*cevapriv), GFP_KERNEL);
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if (!cevapriv)
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return -ENOMEM;
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cevapriv->ahci_pdev = pdev;
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cevapriv->rst = devm_reset_control_get_optional_exclusive(&pdev->dev,
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NULL);
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if (IS_ERR(cevapriv->rst))
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dev_err_probe(&pdev->dev, PTR_ERR(cevapriv->rst),
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"failed to get reset\n");
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hpriv = ahci_platform_get_resources(pdev, 0);
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if (IS_ERR(hpriv))
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return PTR_ERR(hpriv);
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if (!cevapriv->rst) {
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rc = ahci_platform_enable_resources(hpriv);
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if (rc)
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return rc;
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} else {
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int i;
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rc = ahci_platform_enable_clks(hpriv);
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if (rc)
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return rc;
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/* Assert the controller reset */
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reset_control_assert(cevapriv->rst);
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for (i = 0; i < hpriv->nports; i++) {
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rc = phy_init(hpriv->phys[i]);
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if (rc)
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return rc;
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}
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/* De-assert the controller reset */
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reset_control_deassert(cevapriv->rst);
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for (i = 0; i < hpriv->nports; i++) {
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rc = phy_power_on(hpriv->phys[i]);
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if (rc) {
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phy_exit(hpriv->phys[i]);
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return rc;
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}
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}
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}
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if (of_property_read_bool(np, "ceva,broken-gen2"))
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cevapriv->flags = CEVA_FLAG_BROKEN_GEN2;
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/* Read OOB timing value for COMINIT from device-tree */
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if (of_property_read_u8_array(np, "ceva,p0-cominit-params",
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(u8 *)&cevapriv->pp2c[0], 4) < 0) {
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dev_warn(dev, "ceva,p0-cominit-params property not defined\n");
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return -EINVAL;
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}
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if (of_property_read_u8_array(np, "ceva,p1-cominit-params",
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(u8 *)&cevapriv->pp2c[1], 4) < 0) {
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dev_warn(dev, "ceva,p1-cominit-params property not defined\n");
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return -EINVAL;
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}
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/* Read OOB timing value for COMWAKE from device-tree*/
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if (of_property_read_u8_array(np, "ceva,p0-comwake-params",
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(u8 *)&cevapriv->pp3c[0], 4) < 0) {
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dev_warn(dev, "ceva,p0-comwake-params property not defined\n");
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return -EINVAL;
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}
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if (of_property_read_u8_array(np, "ceva,p1-comwake-params",
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(u8 *)&cevapriv->pp3c[1], 4) < 0) {
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dev_warn(dev, "ceva,p1-comwake-params property not defined\n");
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return -EINVAL;
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}
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/* Read phy BURST timing value from device-tree */
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if (of_property_read_u8_array(np, "ceva,p0-burst-params",
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(u8 *)&cevapriv->pp4c[0], 4) < 0) {
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dev_warn(dev, "ceva,p0-burst-params property not defined\n");
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return -EINVAL;
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}
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if (of_property_read_u8_array(np, "ceva,p1-burst-params",
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(u8 *)&cevapriv->pp4c[1], 4) < 0) {
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dev_warn(dev, "ceva,p1-burst-params property not defined\n");
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return -EINVAL;
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}
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/* Read phy RETRY interval timing value from device-tree */
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if (of_property_read_u16_array(np, "ceva,p0-retry-params",
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(u16 *)&cevapriv->pp5c[0], 2) < 0) {
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dev_warn(dev, "ceva,p0-retry-params property not defined\n");
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return -EINVAL;
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}
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if (of_property_read_u16_array(np, "ceva,p1-retry-params",
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(u16 *)&cevapriv->pp5c[1], 2) < 0) {
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dev_warn(dev, "ceva,p1-retry-params property not defined\n");
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return -EINVAL;
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}
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/*
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* Check if CCI is enabled for SATA. The DEV_DMA_COHERENT is returned
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* if CCI is enabled, so check for DEV_DMA_COHERENT.
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*/
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attr = device_get_dma_attr(dev);
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cevapriv->is_cci_enabled = (attr == DEV_DMA_COHERENT);
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hpriv->plat_data = cevapriv;
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/* CEVA specific initialization */
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ahci_ceva_setup(hpriv);
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rc = ahci_platform_init_host(pdev, hpriv, &ahci_ceva_port_info,
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&ahci_platform_sht);
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if (rc)
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goto disable_resources;
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return 0;
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disable_resources:
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ahci_platform_disable_resources(hpriv);
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return rc;
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}
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static int __maybe_unused ceva_ahci_suspend(struct device *dev)
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{
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return ahci_platform_suspend(dev);
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}
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static int __maybe_unused ceva_ahci_resume(struct device *dev)
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{
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struct ata_host *host = dev_get_drvdata(dev);
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struct ahci_host_priv *hpriv = host->private_data;
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int rc;
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rc = ahci_platform_enable_resources(hpriv);
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if (rc)
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return rc;
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/* Configure CEVA specific config before resuming HBA */
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ahci_ceva_setup(hpriv);
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rc = ahci_platform_resume_host(dev);
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if (rc)
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goto disable_resources;
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/* We resumed so update PM runtime state */
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pm_runtime_disable(dev);
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pm_runtime_set_active(dev);
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pm_runtime_enable(dev);
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return 0;
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disable_resources:
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ahci_platform_disable_resources(hpriv);
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return rc;
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}
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static SIMPLE_DEV_PM_OPS(ahci_ceva_pm_ops, ceva_ahci_suspend, ceva_ahci_resume);
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static const struct of_device_id ceva_ahci_of_match[] = {
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{ .compatible = "ceva,ahci-1v84" },
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{},
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};
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MODULE_DEVICE_TABLE(of, ceva_ahci_of_match);
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static struct platform_driver ceva_ahci_driver = {
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.probe = ceva_ahci_probe,
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.remove = ata_platform_remove_one,
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.driver = {
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.name = DRV_NAME,
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.of_match_table = ceva_ahci_of_match,
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.pm = &ahci_ceva_pm_ops,
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},
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};
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module_platform_driver(ceva_ahci_driver);
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MODULE_DESCRIPTION("CEVA AHCI SATA platform driver");
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MODULE_AUTHOR("Xilinx Inc.");
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MODULE_LICENSE("GPL v2");
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