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bcb63314e2
Drop the FSF's postal address from the source code files that typically
contain mostly the license text. Of the 628 removed instances, 578 are
outdated.
The patch has been created with the following command without manual edits:
git grep -l "675 Mass Ave\|59 Temple Place\|51 Franklin St" -- \
drivers/media/ include/media|while read i; do i=$i perl -e '
open(F,"< $ENV{i}");
$a=join("", <F>);
$a =~ s/[ \t]*\*\n.*You should.*\n.*along with.*\n.*(\n.*USA.*$)?\n//m
&& $a =~ s/(^.*)Or, (point your browser to) /$1To obtain the license, $2\n$1/m;
close(F);
open(F, "> $ENV{i}");
print F $a;
close(F);'; done
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
398 lines
9.8 KiB
C
398 lines
9.8 KiB
C
/*
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* Driver for Microtune MT2060 "Single chip dual conversion broadband tuner"
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*
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* Copyright (c) 2006 Olivier DANET <odanet@caramail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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*
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* GNU General Public License for more details.
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*/
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/* In that file, frequencies are expressed in kiloHertz to avoid 32 bits overflows */
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#include <linux/module.h>
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#include <linux/delay.h>
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#include <linux/dvb/frontend.h>
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#include <linux/i2c.h>
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#include <linux/slab.h>
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#include "dvb_frontend.h"
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#include "mt2060.h"
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#include "mt2060_priv.h"
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static int debug;
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module_param(debug, int, 0644);
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MODULE_PARM_DESC(debug, "Turn on/off debugging (default:off).");
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#define dprintk(args...) do { if (debug) {printk(KERN_DEBUG "MT2060: " args); printk("\n"); }} while (0)
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// Reads a single register
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static int mt2060_readreg(struct mt2060_priv *priv, u8 reg, u8 *val)
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{
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struct i2c_msg msg[2] = {
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{ .addr = priv->cfg->i2c_address, .flags = 0, .buf = ®, .len = 1 },
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{ .addr = priv->cfg->i2c_address, .flags = I2C_M_RD, .buf = val, .len = 1 },
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};
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if (i2c_transfer(priv->i2c, msg, 2) != 2) {
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printk(KERN_WARNING "mt2060 I2C read failed\n");
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return -EREMOTEIO;
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}
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return 0;
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}
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// Writes a single register
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static int mt2060_writereg(struct mt2060_priv *priv, u8 reg, u8 val)
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{
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u8 buf[2] = { reg, val };
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struct i2c_msg msg = {
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.addr = priv->cfg->i2c_address, .flags = 0, .buf = buf, .len = 2
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};
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if (i2c_transfer(priv->i2c, &msg, 1) != 1) {
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printk(KERN_WARNING "mt2060 I2C write failed\n");
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return -EREMOTEIO;
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}
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return 0;
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}
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// Writes a set of consecutive registers
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static int mt2060_writeregs(struct mt2060_priv *priv,u8 *buf, u8 len)
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{
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struct i2c_msg msg = {
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.addr = priv->cfg->i2c_address, .flags = 0, .buf = buf, .len = len
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};
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if (i2c_transfer(priv->i2c, &msg, 1) != 1) {
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printk(KERN_WARNING "mt2060 I2C write failed (len=%i)\n",(int)len);
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return -EREMOTEIO;
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}
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return 0;
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}
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// Initialisation sequences
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// LNABAND=3, NUM1=0x3C, DIV1=0x74, NUM2=0x1080, DIV2=0x49
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static u8 mt2060_config1[] = {
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REG_LO1C1,
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0x3F, 0x74, 0x00, 0x08, 0x93
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};
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// FMCG=2, GP2=0, GP1=0
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static u8 mt2060_config2[] = {
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REG_MISC_CTRL,
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0x20, 0x1E, 0x30, 0xff, 0x80, 0xff, 0x00, 0x2c, 0x42
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};
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// VGAG=3, V1CSE=1
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#ifdef MT2060_SPURCHECK
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/* The function below calculates the frequency offset between the output frequency if2
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and the closer cross modulation subcarrier between lo1 and lo2 up to the tenth harmonic */
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static int mt2060_spurcalc(u32 lo1,u32 lo2,u32 if2)
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{
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int I,J;
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int dia,diamin,diff;
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diamin=1000000;
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for (I = 1; I < 10; I++) {
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J = ((2*I*lo1)/lo2+1)/2;
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diff = I*(int)lo1-J*(int)lo2;
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if (diff < 0) diff=-diff;
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dia = (diff-(int)if2);
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if (dia < 0) dia=-dia;
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if (diamin > dia) diamin=dia;
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}
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return diamin;
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}
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#define BANDWIDTH 4000 // kHz
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/* Calculates the frequency offset to add to avoid spurs. Returns 0 if no offset is needed */
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static int mt2060_spurcheck(u32 lo1,u32 lo2,u32 if2)
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{
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u32 Spur,Sp1,Sp2;
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int I,J;
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I=0;
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J=1000;
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Spur=mt2060_spurcalc(lo1,lo2,if2);
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if (Spur < BANDWIDTH) {
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/* Potential spurs detected */
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dprintk("Spurs before : f_lo1: %d f_lo2: %d (kHz)",
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(int)lo1,(int)lo2);
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I=1000;
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Sp1 = mt2060_spurcalc(lo1+I,lo2+I,if2);
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Sp2 = mt2060_spurcalc(lo1-I,lo2-I,if2);
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if (Sp1 < Sp2) {
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J=-J; I=-I; Spur=Sp2;
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} else
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Spur=Sp1;
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while (Spur < BANDWIDTH) {
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I += J;
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Spur = mt2060_spurcalc(lo1+I,lo2+I,if2);
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}
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dprintk("Spurs after : f_lo1: %d f_lo2: %d (kHz)",
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(int)(lo1+I),(int)(lo2+I));
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}
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return I;
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}
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#endif
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#define IF2 36150 // IF2 frequency = 36.150 MHz
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#define FREF 16000 // Quartz oscillator 16 MHz
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static int mt2060_set_params(struct dvb_frontend *fe)
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{
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struct dtv_frontend_properties *c = &fe->dtv_property_cache;
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struct mt2060_priv *priv;
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int i=0;
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u32 freq;
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u8 lnaband;
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u32 f_lo1,f_lo2;
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u32 div1,num1,div2,num2;
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u8 b[8];
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u32 if1;
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priv = fe->tuner_priv;
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if1 = priv->if1_freq;
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b[0] = REG_LO1B1;
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b[1] = 0xFF;
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if (fe->ops.i2c_gate_ctrl)
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fe->ops.i2c_gate_ctrl(fe, 1); /* open i2c_gate */
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mt2060_writeregs(priv,b,2);
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freq = c->frequency / 1000; /* Hz -> kHz */
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f_lo1 = freq + if1 * 1000;
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f_lo1 = (f_lo1 / 250) * 250;
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f_lo2 = f_lo1 - freq - IF2;
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// From the Comtech datasheet, the step used is 50kHz. The tuner chip could be more precise
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f_lo2 = ((f_lo2 + 25) / 50) * 50;
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priv->frequency = (f_lo1 - f_lo2 - IF2) * 1000,
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#ifdef MT2060_SPURCHECK
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// LO-related spurs detection and correction
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num1 = mt2060_spurcheck(f_lo1,f_lo2,IF2);
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f_lo1 += num1;
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f_lo2 += num1;
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#endif
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//Frequency LO1 = 16MHz * (DIV1 + NUM1/64 )
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num1 = f_lo1 / (FREF / 64);
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div1 = num1 / 64;
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num1 &= 0x3f;
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// Frequency LO2 = 16MHz * (DIV2 + NUM2/8192 )
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num2 = f_lo2 * 64 / (FREF / 128);
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div2 = num2 / 8192;
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num2 &= 0x1fff;
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if (freq <= 95000) lnaband = 0xB0; else
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if (freq <= 180000) lnaband = 0xA0; else
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if (freq <= 260000) lnaband = 0x90; else
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if (freq <= 335000) lnaband = 0x80; else
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if (freq <= 425000) lnaband = 0x70; else
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if (freq <= 480000) lnaband = 0x60; else
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if (freq <= 570000) lnaband = 0x50; else
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if (freq <= 645000) lnaband = 0x40; else
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if (freq <= 730000) lnaband = 0x30; else
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if (freq <= 810000) lnaband = 0x20; else lnaband = 0x10;
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b[0] = REG_LO1C1;
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b[1] = lnaband | ((num1 >>2) & 0x0F);
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b[2] = div1;
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b[3] = (num2 & 0x0F) | ((num1 & 3) << 4);
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b[4] = num2 >> 4;
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b[5] = ((num2 >>12) & 1) | (div2 << 1);
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dprintk("IF1: %dMHz",(int)if1);
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dprintk("PLL freq=%dkHz f_lo1=%dkHz f_lo2=%dkHz",(int)freq,(int)f_lo1,(int)f_lo2);
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dprintk("PLL div1=%d num1=%d div2=%d num2=%d",(int)div1,(int)num1,(int)div2,(int)num2);
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dprintk("PLL [1..5]: %2x %2x %2x %2x %2x",(int)b[1],(int)b[2],(int)b[3],(int)b[4],(int)b[5]);
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mt2060_writeregs(priv,b,6);
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//Waits for pll lock or timeout
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i = 0;
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do {
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mt2060_readreg(priv,REG_LO_STATUS,b);
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if ((b[0] & 0x88)==0x88)
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break;
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msleep(4);
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i++;
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} while (i<10);
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if (fe->ops.i2c_gate_ctrl)
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fe->ops.i2c_gate_ctrl(fe, 0); /* close i2c_gate */
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return 0;
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}
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static void mt2060_calibrate(struct mt2060_priv *priv)
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{
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u8 b = 0;
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int i = 0;
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if (mt2060_writeregs(priv,mt2060_config1,sizeof(mt2060_config1)))
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return;
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if (mt2060_writeregs(priv,mt2060_config2,sizeof(mt2060_config2)))
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return;
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/* initialize the clock output */
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mt2060_writereg(priv, REG_VGAG, (priv->cfg->clock_out << 6) | 0x30);
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do {
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b |= (1 << 6); // FM1SS;
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mt2060_writereg(priv, REG_LO2C1,b);
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msleep(20);
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if (i == 0) {
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b |= (1 << 7); // FM1CA;
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mt2060_writereg(priv, REG_LO2C1,b);
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b &= ~(1 << 7); // FM1CA;
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msleep(20);
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}
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b &= ~(1 << 6); // FM1SS
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mt2060_writereg(priv, REG_LO2C1,b);
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msleep(20);
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i++;
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} while (i < 9);
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i = 0;
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while (i++ < 10 && mt2060_readreg(priv, REG_MISC_STAT, &b) == 0 && (b & (1 << 6)) == 0)
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msleep(20);
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if (i <= 10) {
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mt2060_readreg(priv, REG_FM_FREQ, &priv->fmfreq); // now find out, what is fmreq used for :)
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dprintk("calibration was successful: %d", (int)priv->fmfreq);
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} else
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dprintk("FMCAL timed out");
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}
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static int mt2060_get_frequency(struct dvb_frontend *fe, u32 *frequency)
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{
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struct mt2060_priv *priv = fe->tuner_priv;
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*frequency = priv->frequency;
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return 0;
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}
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static int mt2060_get_if_frequency(struct dvb_frontend *fe, u32 *frequency)
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{
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*frequency = IF2 * 1000;
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return 0;
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}
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static int mt2060_init(struct dvb_frontend *fe)
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{
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struct mt2060_priv *priv = fe->tuner_priv;
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int ret;
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if (fe->ops.i2c_gate_ctrl)
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fe->ops.i2c_gate_ctrl(fe, 1); /* open i2c_gate */
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ret = mt2060_writereg(priv, REG_VGAG,
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(priv->cfg->clock_out << 6) | 0x33);
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if (fe->ops.i2c_gate_ctrl)
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fe->ops.i2c_gate_ctrl(fe, 0); /* close i2c_gate */
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return ret;
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}
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static int mt2060_sleep(struct dvb_frontend *fe)
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{
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struct mt2060_priv *priv = fe->tuner_priv;
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int ret;
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if (fe->ops.i2c_gate_ctrl)
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fe->ops.i2c_gate_ctrl(fe, 1); /* open i2c_gate */
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ret = mt2060_writereg(priv, REG_VGAG,
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(priv->cfg->clock_out << 6) | 0x30);
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if (fe->ops.i2c_gate_ctrl)
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fe->ops.i2c_gate_ctrl(fe, 0); /* close i2c_gate */
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return ret;
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}
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static void mt2060_release(struct dvb_frontend *fe)
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{
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kfree(fe->tuner_priv);
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fe->tuner_priv = NULL;
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}
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static const struct dvb_tuner_ops mt2060_tuner_ops = {
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.info = {
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.name = "Microtune MT2060",
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.frequency_min = 48000000,
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.frequency_max = 860000000,
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.frequency_step = 50000,
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},
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.release = mt2060_release,
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.init = mt2060_init,
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.sleep = mt2060_sleep,
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.set_params = mt2060_set_params,
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.get_frequency = mt2060_get_frequency,
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.get_if_frequency = mt2060_get_if_frequency,
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};
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/* This functions tries to identify a MT2060 tuner by reading the PART/REV register. This is hasty. */
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struct dvb_frontend * mt2060_attach(struct dvb_frontend *fe, struct i2c_adapter *i2c, struct mt2060_config *cfg, u16 if1)
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{
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struct mt2060_priv *priv = NULL;
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u8 id = 0;
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priv = kzalloc(sizeof(struct mt2060_priv), GFP_KERNEL);
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if (priv == NULL)
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return NULL;
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priv->cfg = cfg;
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priv->i2c = i2c;
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priv->if1_freq = if1;
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if (fe->ops.i2c_gate_ctrl)
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fe->ops.i2c_gate_ctrl(fe, 1); /* open i2c_gate */
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if (mt2060_readreg(priv,REG_PART_REV,&id) != 0) {
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kfree(priv);
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return NULL;
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}
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if (id != PART_REV) {
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kfree(priv);
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return NULL;
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}
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printk(KERN_INFO "MT2060: successfully identified (IF1 = %d)\n", if1);
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memcpy(&fe->ops.tuner_ops, &mt2060_tuner_ops, sizeof(struct dvb_tuner_ops));
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fe->tuner_priv = priv;
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mt2060_calibrate(priv);
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if (fe->ops.i2c_gate_ctrl)
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fe->ops.i2c_gate_ctrl(fe, 0); /* close i2c_gate */
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return fe;
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}
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EXPORT_SYMBOL(mt2060_attach);
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MODULE_AUTHOR("Olivier DANET");
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MODULE_DESCRIPTION("Microtune MT2060 silicon tuner driver");
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MODULE_LICENSE("GPL");
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