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c499d029d8
This patch adds support for the AD5755, AD5755-1, AD5757, AD5735, AD5737 16 and 14 bit quad-channel DACs. The AD5757/AD5737 only have current outputs, but for the AD5755/AD5757 each of the outputs can be configured to either be a voltage or a current output. We only allow to configure this at device probe time since usually this needs to match the external circuitry and should not be changed on the fly. A few trivial formatting changes on merge. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Jonathan Cameron <jic23@kernel.org>
104 lines
2.7 KiB
C
104 lines
2.7 KiB
C
/*
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* Copyright 2012 Analog Devices Inc.
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*
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* Licensed under the GPL-2.
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*/
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#ifndef __LINUX_PLATFORM_DATA_AD5755_H__
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#define __LINUX_PLATFORM_DATA_AD5755_H__
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enum ad5755_mode {
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AD5755_MODE_VOLTAGE_0V_5V = 0,
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AD5755_MODE_VOLTAGE_0V_10V = 1,
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AD5755_MODE_VOLTAGE_PLUSMINUS_5V = 2,
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AD5755_MODE_VOLTAGE_PLUSMINUS_10V = 3,
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AD5755_MODE_CURRENT_4mA_20mA = 4,
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AD5755_MODE_CURRENT_0mA_20mA = 5,
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AD5755_MODE_CURRENT_0mA_24mA = 6,
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};
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enum ad5755_dc_dc_phase {
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AD5755_DC_DC_PHASE_ALL_SAME_EDGE = 0,
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AD5755_DC_DC_PHASE_A_B_SAME_EDGE_C_D_OPP_EDGE = 1,
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AD5755_DC_DC_PHASE_A_C_SAME_EDGE_B_D_OPP_EDGE = 2,
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AD5755_DC_DC_PHASE_90_DEGREE = 3,
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};
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enum ad5755_dc_dc_freq {
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AD5755_DC_DC_FREQ_250kHZ = 0,
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AD5755_DC_DC_FREQ_410kHZ = 1,
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AD5755_DC_DC_FREQ_650kHZ = 2,
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};
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enum ad5755_dc_dc_maxv {
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AD5755_DC_DC_MAXV_23V = 0,
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AD5755_DC_DC_MAXV_24V5 = 1,
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AD5755_DC_DC_MAXV_27V = 2,
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AD5755_DC_DC_MAXV_29V5 = 3,
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};
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enum ad5755_slew_rate {
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AD5755_SLEW_RATE_64k = 0,
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AD5755_SLEW_RATE_32k = 1,
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AD5755_SLEW_RATE_16k = 2,
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AD5755_SLEW_RATE_8k = 3,
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AD5755_SLEW_RATE_4k = 4,
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AD5755_SLEW_RATE_2k = 5,
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AD5755_SLEW_RATE_1k = 6,
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AD5755_SLEW_RATE_500 = 7,
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AD5755_SLEW_RATE_250 = 8,
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AD5755_SLEW_RATE_125 = 9,
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AD5755_SLEW_RATE_64 = 10,
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AD5755_SLEW_RATE_32 = 11,
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AD5755_SLEW_RATE_16 = 12,
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AD5755_SLEW_RATE_8 = 13,
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AD5755_SLEW_RATE_4 = 14,
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AD5755_SLEW_RATE_0_5 = 15,
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};
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enum ad5755_slew_step_size {
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AD5755_SLEW_STEP_SIZE_1 = 0,
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AD5755_SLEW_STEP_SIZE_2 = 1,
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AD5755_SLEW_STEP_SIZE_4 = 2,
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AD5755_SLEW_STEP_SIZE_8 = 3,
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AD5755_SLEW_STEP_SIZE_16 = 4,
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AD5755_SLEW_STEP_SIZE_32 = 5,
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AD5755_SLEW_STEP_SIZE_64 = 6,
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AD5755_SLEW_STEP_SIZE_128 = 7,
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AD5755_SLEW_STEP_SIZE_256 = 8,
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};
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/**
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* struct ad5755_platform_data - AD5755 DAC driver platform data
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* @ext_dc_dc_compenstation_resistor: Whether an external DC-DC converter
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* compensation register is used.
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* @dc_dc_phase: DC-DC converter phase.
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* @dc_dc_freq: DC-DC converter frequency.
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* @dc_dc_maxv: DC-DC maximum allowed boost voltage.
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* @dac.mode: The mode to be used for the DAC output.
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* @dac.ext_current_sense_resistor: Whether an external current sense resistor
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* is used.
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* @dac.enable_voltage_overrange: Whether to enable 20% voltage output overrange.
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* @dac.slew.enable: Whether to enable digital slew.
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* @dac.slew.rate: Slew rate of the digital slew.
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* @dac.slew.step_size: Slew step size of the digital slew.
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**/
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struct ad5755_platform_data {
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bool ext_dc_dc_compenstation_resistor;
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enum ad5755_dc_dc_phase dc_dc_phase;
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enum ad5755_dc_dc_freq dc_dc_freq;
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enum ad5755_dc_dc_maxv dc_dc_maxv;
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struct {
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enum ad5755_mode mode;
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bool ext_current_sense_resistor;
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bool enable_voltage_overrange;
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struct {
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bool enable;
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enum ad5755_slew_rate rate;
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enum ad5755_slew_step_size step_size;
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} slew;
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} dac[4];
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};
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#endif
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