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bbde310474
Use standard V4L2 control to get pixel clock rate from a sensor linked in the media controller pipeline. Then calculate clock rates on CSIPHY, CSID and VFE to use the lowest possible. If the currnet pixel clock rate of the sensor cannot be read then use the highest possible. This case covers also the CSID test generator usage. If VFE is already powered on by another pipeline, check that the current VFE clock rate is high enough for the new pipeline. If not return busy error code as VFE clock rate cannot be changed while VFE is running. Signed-off-by: Todor Tomov <todor.tomov@linaro.org> Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com> |
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| .. | ||
| cec | ||
| common | ||
| dvb-core | ||
| dvb-frontends | ||
| firewire | ||
| i2c | ||
| mmc | ||
| pci | ||
| platform | ||
| radio | ||
| rc | ||
| spi | ||
| tuners | ||
| usb | ||
| v4l2-core | ||
| Kconfig | ||
| Makefile | ||
| media-device.c | ||
| media-devnode.c | ||
| media-entity.c | ||