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61f684ec07
The merge-tree version of LOADBASE actually loads the whole given address from the toc for ppc64. The matching OFF macro adjust for this, using an offset of 0 for ppc64, but we weren't using that in power4_idle. Signed-off-by: David Gibson <dwg@au1.ibm.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
79 lines
1.9 KiB
ArmAsm
79 lines
1.9 KiB
ArmAsm
/*
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* This file contains the power_save function for 6xx & 7xxx CPUs
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* rewritten in assembler
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*
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* Warning ! This code assumes that if your machine has a 750fx
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* it will have PLL 1 set to low speed mode (used during NAP/DOZE).
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* if this is not the case some additional changes will have to
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* be done to check a runtime var (a bit like powersave-nap)
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#include <linux/config.h>
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#include <linux/threads.h>
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#include <asm/processor.h>
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#include <asm/page.h>
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#include <asm/cputable.h>
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#include <asm/thread_info.h>
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#include <asm/ppc_asm.h>
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#include <asm/asm-offsets.h>
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#undef DEBUG
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.text
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/*
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* Here is the power_save_6xx function. This could eventually be
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* split into several functions & changing the function pointer
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* depending on the various features.
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*/
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_GLOBAL(power4_idle)
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BEGIN_FTR_SECTION
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blr
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END_FTR_SECTION_IFCLR(CPU_FTR_CAN_NAP)
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/* We must dynamically check for the NAP feature as it
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* can be cleared by CPU init after the fixups are done
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*/
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LOADBASE(r3,cur_cpu_spec)
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ld r4,OFF(cur_cpu_spec)(r3)
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ld r4,CPU_SPEC_FEATURES(r4)
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andi. r0,r4,CPU_FTR_CAN_NAP
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beqlr
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/* Now check if user or arch enabled NAP mode */
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LOADBASE(r3,powersave_nap)
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lwz r4,OFF(powersave_nap)(r3)
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cmpwi 0,r4,0
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beqlr
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/* Clear MSR:EE */
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mfmsr r7
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li r4,0
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ori r4,r4,MSR_EE
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andc r0,r7,r4
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mtmsrd r0
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/* Check current_thread_info()->flags */
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clrrdi r4,r1,THREAD_SHIFT
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ld r4,TI_FLAGS(r4)
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andi. r0,r4,_TIF_NEED_RESCHED
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beq 1f
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mtmsrd r7 /* out of line this ? */
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blr
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1:
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/* Go to NAP now */
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BEGIN_FTR_SECTION
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DSSALL
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sync
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END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
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oris r7,r7,MSR_POW@h
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sync
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isync
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mtmsrd r7
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isync
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sync
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blr
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