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linux-next/drivers/clk/meson
Martin Blumenstingl bb6eddd1d2 clk: meson: meson8b: use the HHI syscon if available
The clock controller is located in a register range (called "HHI") which
contains more than just registers for the clock controller. Known
consumers of the HHI register range are:
- the clock controller
- a reset controller
- temperature sensor calibration coefficient (TSC) (only on Meson8b and
  Meson8m2)
- HDMI controller

The main reason for using a syscon is the "temperature sensor
calibration coefficient" which has to be set for the built-in temperature
sensor to work correctly. Four TSC bits are located in the SAR ADC's
register space. However on Meson8b and Meson8m2 there is a fifth TSC bit
which is unfortunately located in the HHI register space. To be more
precise, bit 9 of the HHI_DPLL_TOP_0 register (which sits right between
the HHI_SYS_PLL and HHI_VID_PLL registers).

Get the regmap from the parent (HHI syscon) node to support all
functionality of the HHI register range. Backwards compatibility with
old .dtbs is ensured by falling back to parsing the registers just like
before this change.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Link: https://lkml.kernel.org/r/20181028120859.5735-3-martin.blumenstingl@googlemail.com
2018-11-23 15:11:56 +01:00
..
axg-aoclk.c clk: meson-axg: Add AO Clock and Reset controller driver 2018-05-15 14:19:43 +02:00
axg-aoclk.h clk: meson-axg: Add AO Clock and Reset controller driver 2018-05-15 14:19:43 +02:00
axg-audio.c clk: meson: axg: round audio system master clocks down 2018-09-26 12:02:00 +02:00
axg-audio.h clk: meson: axg: add the audio clock controller driver 2018-07-09 13:48:26 +02:00
axg.c clk: meson-axg: pcie: drop the mpll3 clock parent 2018-09-26 12:02:00 +02:00
axg.h clk: meson: clk-pll: remove od parameters 2018-09-26 12:01:57 +02:00
clk-mpll.c clk: meson: mpll: add round closest support 2018-05-21 11:31:29 +02:00
clk-phase.c clk: meson: add clk-phase clock driver 2018-07-09 13:47:22 +02:00
clk-pll.c clk: meson: clk-pll: drop hard-coded rates from pll tables 2018-09-26 12:02:00 +02:00
clk-regmap.c This time we have a good set of changes to the core framework that do some 2018-06-09 12:06:24 -07:00
clk-regmap.h clk: meson: use SPDX license identifiers consistently 2018-05-18 12:08:29 +02:00
clk-triphase.c clk: meson: add triple phase clock driver 2018-07-09 13:47:22 +02:00
clkc-audio.h clk: meson: add axg audio sclk divider driver 2018-07-09 13:48:25 +02:00
clkc.h clk: meson: Add vid_pll divider driver 2018-11-23 15:11:56 +01:00
gxbb-aoclk-32k.c clk: meson: use SPDX license identifiers consistently 2018-05-18 12:08:29 +02:00
gxbb-aoclk.c clk: meson: use SPDX license identifiers consistently 2018-05-18 12:08:29 +02:00
gxbb-aoclk.h This time we have a good set of changes to the core framework that do some 2018-06-09 12:06:24 -07:00
gxbb.c clk: meson-gxbb: Add video clocks 2018-11-23 15:11:56 +01:00
gxbb.h dt-bindings: clk: meson-gxbb: Add Video clock bindings 2018-11-23 15:11:56 +01:00
Kconfig clk: meson: axg: add the audio clock controller driver 2018-07-09 13:48:26 +02:00
Makefile clk: meson: Add vid_pll divider driver 2018-11-23 15:11:56 +01:00
meson8b.c clk: meson: meson8b: use the HHI syscon if available 2018-11-23 15:11:56 +01:00
meson8b.h clk: meson: clk-pll: remove od parameters 2018-09-26 12:01:57 +02:00
meson-aoclk.c clk: meson: aoclk: refactor common code into dedicated file 2018-05-15 14:19:42 +02:00
meson-aoclk.h clk: meson: aoclk: refactor common code into dedicated file 2018-05-15 14:19:42 +02:00
sclk-div.c clk: meson: add axg audio sclk divider driver 2018-07-09 13:48:25 +02:00
vid-pll-div.c clk: meson: Add vid_pll divider driver 2018-11-23 15:11:56 +01:00