mirror of
https://github.com/edk2-porting/linux-next.git
synced 2024-12-28 23:23:55 +08:00
6cd94d5e57
New and updated SoC support, notable changes include: * bcm: brcmstb SMP support * bcm: initial iproc/cygnus support * exynos: Exynos4415 SoC support * exynos: PMU and suspend support for Exynos5420 * exynos: PMU support for Exynos3250 * exynos: pm related maintenance * imx: new LS1021A SoC support * imx: vybrid 610 global timer support * integrator: convert to using multiplatform configuration * mediatek: earlyprintk support for mt8127/mt8135 * meson: meson8 soc and l2 cache controller support * mvebu: Armada 38x CPU hotplug support * mvebu: drop support for prerelease Armada 375 Z1 stepping * mvebu: extended suspend support, now works on Armada 370/XP * omap: hwmod related maintenance * omap: prcm cleanup * pxa: initial pxa27x DT handling * rockchip: SMP support for rk3288 * rockchip: add cpu frequency scaling support * shmobile: r8a7740 power domain support * shmobile: various small restart, timer, pci apmu changes * sunxi: Allwinner A80 (sun9i) earlyprintk support * ux500: power domain support Overall, a significant chunk of changes, coming mostly from the usual suspects: omap, shmobile, samsung and mvebu, all of which already contain a lot of platform specific code in arch/arm. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.12 (GNU/Linux) iQIVAwUAVIcjyGCrR//JCVInAQJJCRAA1Tm+HZGiAiTvXEAcm/T9tIA08uqtawHt cqyEAUyrnE8QxE4EhUd2pTw4EunVusqKF5EsDxOzw7b3ukUdLAWZE7bqBOSIJLqn hrfsQQ8dXLbyC7T/CHPnBVeM+pn9LiIc9qzpZ0YToiMnHBBI4vKFQntBjd31yoRE hN08I6AmDjQolOzzlqR1fuM0uZaKiHIcytdauTt3Vfqgg7FTHcTy3u1kClHTR1Lp m/KuDothGpR5OKjSnUQz7EO5V3KJEnaKey8z2xM1a7DLLAvJ6r2+DUaDopv9Dbz1 W/V3H7fi5tLvillVa8xmlmzqWZbPc1xw8MWqvHZSWIMRZqloAHpC1VWKn0ZuH4SW 5Bj4ubSrpYjJxjKYfrxtjmuzru3A2jWBNTSP5A4nsny0C3AUsXkfRmRS0VNdegF8 sUdQ1MF8vEMpQT3QPH88+ccFHeIgqbcayhKqLPf7r8q0kwlym5N7Y2amU2A/O6qz +324r+yzfSA70VgJZ5EhXxWVDOPB4Lc8EtoWnH6T/kjncIMwzEsbEbyB3X1OaREW pVn3PNo06VjHLYoiHX+8G99pOFR/JZvaQs6jGCXLs+Orjp5WfP+kafkWqcB5GAKU Pfd3AQsl6rKAITdu0XsTdPiICNS4CmBiWYPepQsTa3pQaNgB7fwZNQKelNRIdGc+ dF1lnQ7CXLQ= =lFoH -----END PGP SIGNATURE----- Merge tag 'soc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC platform changes from Arnd Bergmann: "New and updated SoC support, notable changes include: - bcm: brcmstb SMP support initial iproc/cygnus support - exynos: Exynos4415 SoC support PMU and suspend support for Exynos5420 PMU support for Exynos3250 pm related maintenance - imx: new LS1021A SoC support vybrid 610 global timer support - integrator: convert to using multiplatform configuration - mediatek: earlyprintk support for mt8127/mt8135 - meson: meson8 soc and l2 cache controller support - mvebu: Armada 38x CPU hotplug support drop support for prerelease Armada 375 Z1 stepping extended suspend support, now works on Armada 370/XP - omap: hwmod related maintenance prcm cleanup - pxa: initial pxa27x DT handling - rockchip: SMP support for rk3288 add cpu frequency scaling support - shmobile: r8a7740 power domain support various small restart, timer, pci apmu changes - sunxi: Allwinner A80 (sun9i) earlyprintk support - ux500: power domain support Overall, a significant chunk of changes, coming mostly from the usual suspects: omap, shmobile, samsung and mvebu, all of which already contain a lot of platform specific code in arch/arm" * tag 'soc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (187 commits) ARM: mvebu: use the cpufreq-dt platform_data for independent clocks soc: integrator: Add terminating entry for integrator_cm_match ARM: mvebu: add SDRAM controller description for Armada XP ARM: mvebu: adjust mbus controller description on Armada 370/XP ARM: mvebu: add suspend/resume DT information for Armada XP GP ARM: mvebu: synchronize secondary CPU clocks on resume ARM: mvebu: make sure MMU is disabled in armada_370_xp_cpu_resume ARM: mvebu: Armada XP GP specific suspend/resume code ARM: mvebu: reserve the first 10 KB of each memory bank for suspend/resume ARM: mvebu: implement suspend/resume support for Armada XP clk: mvebu: add suspend/resume for gatable clocks bus: mvebu-mbus: provide a mechanism to save SDRAM window configuration bus: mvebu-mbus: suspend/resume support clocksource: time-armada-370-xp: add suspend/resume support irqchip: armada-370-xp: Add suspend/resume support ARM: add lolevel debug support for asm9260 ARM: add mach-asm9260 ARM: EXYNOS: use u8 for val[] in struct exynos_pmu_conf power: reset: imx-snvs-poweroff: add power off driver for i.mx6 ARM: imx: temporarily remove CONFIG_SOC_FSL from LS1021A ...
101 lines
2.7 KiB
C
101 lines
2.7 KiB
C
/*
|
|
* SH-Mobile Timer
|
|
*
|
|
* Copyright (C) 2010 Magnus Damm
|
|
* Copyright (C) 2002 - 2009 Paul Mundt
|
|
*
|
|
* This program is free software; you can redistribute it and/or modify
|
|
* it under the terms of the GNU General Public License as published by
|
|
* the Free Software Foundation; version 2 of the License.
|
|
*
|
|
* This program is distributed in the hope that it will be useful,
|
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
* GNU General Public License for more details.
|
|
*/
|
|
#include <linux/platform_device.h>
|
|
#include <linux/clocksource.h>
|
|
#include <linux/delay.h>
|
|
#include <linux/of_address.h>
|
|
|
|
static void __init shmobile_setup_delay_hz(unsigned int max_cpu_core_hz,
|
|
unsigned int mult, unsigned int div)
|
|
{
|
|
/* calculate a worst-case loops-per-jiffy value
|
|
* based on maximum cpu core hz setting and the
|
|
* __delay() implementation in arch/arm/lib/delay.S
|
|
*
|
|
* this will result in a longer delay than expected
|
|
* when the cpu core runs on lower frequencies.
|
|
*/
|
|
|
|
unsigned int value = HZ * div / mult;
|
|
|
|
if (!preset_lpj)
|
|
preset_lpj = max_cpu_core_hz / value;
|
|
}
|
|
|
|
void __init shmobile_init_delay(void)
|
|
{
|
|
struct device_node *np, *cpus;
|
|
bool is_a7_a8_a9 = false;
|
|
bool is_a15 = false;
|
|
bool has_arch_timer = false;
|
|
u32 max_freq = 0;
|
|
|
|
cpus = of_find_node_by_path("/cpus");
|
|
if (!cpus)
|
|
return;
|
|
|
|
for_each_child_of_node(cpus, np) {
|
|
u32 freq;
|
|
|
|
if (!of_property_read_u32(np, "clock-frequency", &freq))
|
|
max_freq = max(max_freq, freq);
|
|
|
|
if (of_device_is_compatible(np, "arm,cortex-a8") ||
|
|
of_device_is_compatible(np, "arm,cortex-a9")) {
|
|
is_a7_a8_a9 = true;
|
|
} else if (of_device_is_compatible(np, "arm,cortex-a7")) {
|
|
is_a7_a8_a9 = true;
|
|
has_arch_timer = true;
|
|
} else if (of_device_is_compatible(np, "arm,cortex-a15")) {
|
|
is_a15 = true;
|
|
has_arch_timer = true;
|
|
}
|
|
}
|
|
|
|
of_node_put(cpus);
|
|
|
|
if (!max_freq)
|
|
return;
|
|
|
|
if (!has_arch_timer || !IS_ENABLED(CONFIG_ARM_ARCH_TIMER)) {
|
|
if (is_a7_a8_a9)
|
|
shmobile_setup_delay_hz(max_freq, 1, 3);
|
|
else if (is_a15)
|
|
shmobile_setup_delay_hz(max_freq, 2, 4);
|
|
}
|
|
}
|
|
|
|
static void __init shmobile_late_time_init(void)
|
|
{
|
|
/*
|
|
* Make sure all compiled-in early timers register themselves.
|
|
*
|
|
* Run probe() for two "earlytimer" devices, these will be the
|
|
* clockevents and clocksource devices respectively. In the event
|
|
* that only a clockevents device is available, we -ENODEV on the
|
|
* clocksource and the jiffies clocksource is used transparently
|
|
* instead. No error handling is necessary here.
|
|
*/
|
|
early_platform_driver_register_all("earlytimer");
|
|
early_platform_driver_probe("earlytimer", 2, 0);
|
|
}
|
|
|
|
void __init shmobile_earlytimer_init(void)
|
|
{
|
|
late_time_init = shmobile_late_time_init;
|
|
}
|
|
|