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The memory controller on NVIDIA Tegra exposes various knobs that can be used to tune the behaviour of the clients attached to it. In addition, the memory controller implements an SMMU (IOMMU) which can translate I/O virtual addresses to physical addresses for clients. This is useful for scatter-gather operation on devices that don't support it natively and for virtualization or process separation. Signed-off-by: Thierry Reding <treding@nvidia.com>
37 lines
1.1 KiB
Plaintext
37 lines
1.1 KiB
Plaintext
NVIDIA Tegra Memory Controller device tree bindings
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===================================================
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Required properties:
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- compatible: Should be "nvidia,tegra<chip>-mc"
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- reg: Physical base address and length of the controller's registers.
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- clocks: Must contain an entry for each entry in clock-names.
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See ../clocks/clock-bindings.txt for details.
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- clock-names: Must include the following entries:
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- mc: the module's clock input
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- interrupts: The interrupt outputs from the controller.
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- #iommu-cells: Should be 1. The single cell of the IOMMU specifier defines
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the SWGROUP of the master.
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This device implements an IOMMU that complies with the generic IOMMU binding.
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See ../iommu/iommu.txt for details.
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Example:
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--------
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mc: memory-controller@0,70019000 {
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compatible = "nvidia,tegra124-mc";
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reg = <0x0 0x70019000 0x0 0x1000>;
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clocks = <&tegra_car TEGRA124_CLK_MC>;
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clock-names = "mc";
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interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
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#iommu-cells = <1>;
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};
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sdhci@0,700b0000 {
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compatible = "nvidia,tegra124-sdhci";
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...
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iommus = <&mc TEGRA_SWGROUP_SDMMC1A>;
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};
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