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linux-next/arch/x86/kvm
Will Auld ba904635d4 KVM: x86: Emulate IA32_TSC_ADJUST MSR
CPUID.7.0.EBX[1]=1 indicates IA32_TSC_ADJUST MSR 0x3b is supported

Basic design is to emulate the MSR by allowing reads and writes to a guest
vcpu specific location to store the value of the emulated MSR while adding
the value to the vmcs tsc_offset. In this way the IA32_TSC_ADJUST value will
be included in all reads to the TSC MSR whether through rdmsr or rdtsc. This
is of course as long as the "use TSC counter offsetting" VM-execution control
is enabled as well as the IA32_TSC_ADJUST control.

However, because hardware will only return the TSC + IA32_TSC_ADJUST +
vmsc tsc_offset for a guest process when it does and rdtsc (with the correct
settings) the value of our virtualized IA32_TSC_ADJUST must be stored in one
of these three locations. The argument against storing it in the actual MSR
is performance. This is likely to be seldom used while the save/restore is
required on every transition. IA32_TSC_ADJUST was created as a way to solve
some issues with writing TSC itself so that is not an option either.

The remaining option, defined above as our solution has the problem of
returning incorrect vmcs tsc_offset values (unless we intercept and fix, not
done here) as mentioned above. However, more problematic is that storing the
data in vmcs tsc_offset will have a different semantic effect on the system
than does using the actual MSR. This is illustrated in the following example:

The hypervisor set the IA32_TSC_ADJUST, then the guest sets it and a guest
process performs a rdtsc. In this case the guest process will get
TSC + IA32_TSC_ADJUST_hyperviser + vmsc tsc_offset including
IA32_TSC_ADJUST_guest. While the total system semantics changed the semantics
as seen by the guest do not and hence this will not cause a problem.

Signed-off-by: Will Auld <will.auld@intel.com>
Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
2012-11-30 18:29:30 -02:00
..
cpuid.c KVM: x86: Emulate IA32_TSC_ADJUST MSR 2012-11-30 18:29:30 -02:00
cpuid.h KVM: x86: Emulate IA32_TSC_ADJUST MSR 2012-11-30 18:29:30 -02:00
emulate.c KVM: emulator: optimize "rep ins" handling 2012-09-06 18:07:38 +03:00
i8254.c KVM: fold kvm_pit_timer into kvm_kpit_state 2012-08-01 00:21:07 -03:00
i8254.h KVM: fold kvm_pit_timer into kvm_kpit_state 2012-08-01 00:21:07 -03:00
i8259.c KVM: PIC: fix use of uninitialised variable. 2012-09-04 15:44:42 +03:00
irq.c KVM: fix typo in copyright notice 2010-10-24 10:53:14 +02:00
irq.h KVM: switch to symbolic name for irq_states size 2012-07-20 16:12:16 -03:00
Kconfig KVM: Depend on HIGH_RES_TIMERS 2012-09-10 11:10:03 +03:00
kvm_cache_regs.h KVM: MMU: Do not unconditionally read PDPTE from guest memory 2011-09-25 19:18:01 +03:00
lapic.c KVM: x86: pass host_tsc to read_l1_tsc 2012-11-27 23:29:11 -02:00
lapic.h KVM: optimize apic interrupt delivery 2012-09-20 15:05:26 +03:00
Makefile KVM: Remove internal timer abstraction 2012-08-01 00:21:06 -03:00
mmu_audit.c KVM: do not release the error pfn 2012-08-06 16:04:57 +03:00
mmu.c KVM: do not treat noslot pfn as a error pfn 2012-10-29 20:31:04 -02:00
mmu.h KVM: MMU: Optimize is_last_gpte() 2012-09-20 13:00:09 +03:00
mmutrace.h KVM: MMU: fix kvm_mmu_pagetable_walk tracepoint 2012-07-11 16:51:22 +03:00
paging_tmpl.h KVM: do not treat noslot pfn as a error pfn 2012-10-29 20:31:04 -02:00
pmu.c Merge branch 'queue' into next 2012-07-26 11:54:21 +03:00
svm.c KVM: x86: Emulate IA32_TSC_ADJUST MSR 2012-11-30 18:29:30 -02:00
trace.h KVM: x86: require matched TSC offsets for master clock 2012-11-27 23:29:15 -02:00
tss.h KVM: x86: hardware task switching support 2008-04-27 12:00:39 +03:00
vmx.c KVM: x86: Emulate IA32_TSC_ADJUST MSR 2012-11-30 18:29:30 -02:00
x86.c KVM: x86: Emulate IA32_TSC_ADJUST MSR 2012-11-30 18:29:30 -02:00
x86.h KVM: x86: Add code to track call origin for msr assignment 2012-11-30 18:26:12 -02:00