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4e969010c5
As discussed on linux-arm-kernel, we want to avoid relative includes for the arch/arm/*omap* code: http://www.spinics.net/lists/linux-omap/msg80520.html Note that eventually when the omap1 specific drivers are fixed to not use cpu_is_omap macros and not depend on mach/hardware.h, this patch can be reverted and these headers can be local. But since just fixing the drivers for omap2+ is already a big enough hassle, let's deal with that properly first. [tony@atomide.com: also drop unused include for ispvideo.c] Signed-off-by: Tony Lindgren <tony@atomide.com>
371 lines
9.1 KiB
ArmAsm
371 lines
9.1 KiB
ArmAsm
/*
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* linux/arch/arm/mach-omap1/sleep.S
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*
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* Low-level OMAP7XX/1510/1610 sleep/wakeUp support
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*
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* Initial SA1110 code:
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* Copyright (c) 2001 Cliff Brake <cbrake@accelent.com>
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*
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* Adapted for PXA by Nicolas Pitre:
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* Copyright (c) 2002 Monta Vista Software, Inc.
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*
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* Support for OMAP1510/1610 by Dirk Behme <dirk.behme@de.bosch.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
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* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
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* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include <linux/linkage.h>
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#include <asm/assembler.h>
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#include <mach/hardware.h>
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#include "iomap.h"
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#include "pm.h"
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.text
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/*
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* Forces OMAP into deep sleep state
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*
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* omapXXXX_cpu_suspend()
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*
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* The values of the registers ARM_IDLECT1 and ARM_IDLECT2 are passed
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* as arg0 and arg1 from caller. arg0 is stored in register r0 and arg1
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* in register r1.
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*
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* Note: This code get's copied to internal SRAM at boot. When the OMAP
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* wakes up it continues execution at the point it went to sleep.
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*
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* Note: Because of errata work arounds we have processor specific functions
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* here. They are mostly the same, but slightly different.
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*
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*/
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#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
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.align 3
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ENTRY(omap7xx_cpu_suspend)
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@ save registers on stack
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stmfd sp!, {r0 - r12, lr}
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@ Drain write cache
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mov r4, #0
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mcr p15, 0, r0, c7, c10, 4
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nop
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@ load base address of Traffic Controller
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mov r6, #TCMIF_ASM_BASE & 0xff000000
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orr r6, r6, #TCMIF_ASM_BASE & 0x00ff0000
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orr r6, r6, #TCMIF_ASM_BASE & 0x0000ff00
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@ prepare to put SDRAM into self-refresh manually
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ldr r7, [r6, #EMIFF_SDRAM_CONFIG_ASM_OFFSET & 0xff]
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orr r9, r7, #SELF_REFRESH_MODE & 0xff000000
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orr r9, r9, #SELF_REFRESH_MODE & 0x000000ff
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str r9, [r6, #EMIFF_SDRAM_CONFIG_ASM_OFFSET & 0xff]
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@ prepare to put EMIFS to Sleep
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ldr r8, [r6, #EMIFS_CONFIG_ASM_OFFSET & 0xff]
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orr r9, r8, #IDLE_EMIFS_REQUEST & 0xff
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str r9, [r6, #EMIFS_CONFIG_ASM_OFFSET & 0xff]
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@ load base address of ARM_IDLECT1 and ARM_IDLECT2
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mov r4, #CLKGEN_REG_ASM_BASE & 0xff000000
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orr r4, r4, #CLKGEN_REG_ASM_BASE & 0x00ff0000
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orr r4, r4, #CLKGEN_REG_ASM_BASE & 0x0000ff00
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@ turn off clock domains
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@ do not disable PERCK (0x04)
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mov r5, #OMAP7XX_IDLECT2_SLEEP_VAL & 0xff
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orr r5, r5, #OMAP7XX_IDLECT2_SLEEP_VAL & 0xff00
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strh r5, [r4, #ARM_IDLECT2_ASM_OFFSET & 0xff]
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@ request ARM idle
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mov r3, #OMAP7XX_IDLECT1_SLEEP_VAL & 0xff
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orr r3, r3, #OMAP7XX_IDLECT1_SLEEP_VAL & 0xff00
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strh r3, [r4, #ARM_IDLECT1_ASM_OFFSET & 0xff]
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@ disable instruction cache
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mrc p15, 0, r9, c1, c0, 0
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bic r2, r9, #0x1000
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mcr p15, 0, r2, c1, c0, 0
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nop
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/*
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* Let's wait for the next wake up event to wake us up. r0 can't be
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* used here because r0 holds ARM_IDLECT1
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*/
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mov r2, #0
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mcr p15, 0, r2, c7, c0, 4 @ wait for interrupt
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/*
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* omap7xx_cpu_suspend()'s resume point.
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*
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* It will just start executing here, so we'll restore stuff from the
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* stack.
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*/
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@ re-enable Icache
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mcr p15, 0, r9, c1, c0, 0
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@ reset the ARM_IDLECT1 and ARM_IDLECT2.
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strh r1, [r4, #ARM_IDLECT2_ASM_OFFSET & 0xff]
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strh r0, [r4, #ARM_IDLECT1_ASM_OFFSET & 0xff]
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@ Restore EMIFF controls
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str r7, [r6, #EMIFF_SDRAM_CONFIG_ASM_OFFSET & 0xff]
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str r8, [r6, #EMIFS_CONFIG_ASM_OFFSET & 0xff]
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@ restore regs and return
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ldmfd sp!, {r0 - r12, pc}
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ENTRY(omap7xx_cpu_suspend_sz)
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.word . - omap7xx_cpu_suspend
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#endif /* CONFIG_ARCH_OMAP730 || CONFIG_ARCH_OMAP850 */
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#ifdef CONFIG_ARCH_OMAP15XX
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.align 3
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ENTRY(omap1510_cpu_suspend)
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@ save registers on stack
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stmfd sp!, {r0 - r12, lr}
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@ load base address of Traffic Controller
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mov r4, #TCMIF_ASM_BASE & 0xff000000
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orr r4, r4, #TCMIF_ASM_BASE & 0x00ff0000
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orr r4, r4, #TCMIF_ASM_BASE & 0x0000ff00
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@ work around errata of OMAP1510 PDE bit for TC shut down
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@ clear PDE bit
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ldr r5, [r4, #EMIFS_CONFIG_ASM_OFFSET & 0xff]
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bic r5, r5, #PDE_BIT & 0xff
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str r5, [r4, #EMIFS_CONFIG_ASM_OFFSET & 0xff]
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@ set PWD_EN bit
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and r5, r5, #PWD_EN_BIT & 0xff
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str r5, [r4, #EMIFS_CONFIG_ASM_OFFSET & 0xff]
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@ prepare to put SDRAM into self-refresh manually
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ldr r5, [r4, #EMIFF_SDRAM_CONFIG_ASM_OFFSET & 0xff]
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orr r5, r5, #SELF_REFRESH_MODE & 0xff000000
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orr r5, r5, #SELF_REFRESH_MODE & 0x000000ff
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str r5, [r4, #EMIFF_SDRAM_CONFIG_ASM_OFFSET & 0xff]
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@ prepare to put EMIFS to Sleep
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ldr r5, [r4, #EMIFS_CONFIG_ASM_OFFSET & 0xff]
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orr r5, r5, #IDLE_EMIFS_REQUEST & 0xff
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str r5, [r4, #EMIFS_CONFIG_ASM_OFFSET & 0xff]
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@ load base address of ARM_IDLECT1 and ARM_IDLECT2
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mov r4, #CLKGEN_REG_ASM_BASE & 0xff000000
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orr r4, r4, #CLKGEN_REG_ASM_BASE & 0x00ff0000
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orr r4, r4, #CLKGEN_REG_ASM_BASE & 0x0000ff00
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@ turn off clock domains
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mov r5, #OMAP1510_IDLE_CLOCK_DOMAINS & 0xff
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orr r5, r5, #OMAP1510_IDLE_CLOCK_DOMAINS & 0xff00
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strh r5, [r4, #ARM_IDLECT2_ASM_OFFSET & 0xff]
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@ request ARM idle
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mov r3, #OMAP1510_DEEP_SLEEP_REQUEST & 0xff
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orr r3, r3, #OMAP1510_DEEP_SLEEP_REQUEST & 0xff00
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strh r3, [r4, #ARM_IDLECT1_ASM_OFFSET & 0xff]
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mov r5, #IDLE_WAIT_CYCLES & 0xff
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orr r5, r5, #IDLE_WAIT_CYCLES & 0xff00
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l_1510_2:
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subs r5, r5, #1
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bne l_1510_2
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/*
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* Let's wait for the next wake up event to wake us up. r0 can't be
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* used here because r0 holds ARM_IDLECT1
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*/
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mov r2, #0
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mcr p15, 0, r2, c7, c0, 4 @ wait for interrupt
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/*
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* omap1510_cpu_suspend()'s resume point.
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*
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* It will just start executing here, so we'll restore stuff from the
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* stack, reset the ARM_IDLECT1 and ARM_IDLECT2.
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*/
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strh r1, [r4, #ARM_IDLECT2_ASM_OFFSET & 0xff]
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strh r0, [r4, #ARM_IDLECT1_ASM_OFFSET & 0xff]
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@ restore regs and return
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ldmfd sp!, {r0 - r12, pc}
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ENTRY(omap1510_cpu_suspend_sz)
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.word . - omap1510_cpu_suspend
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#endif /* CONFIG_ARCH_OMAP15XX */
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#if defined(CONFIG_ARCH_OMAP16XX)
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.align 3
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ENTRY(omap1610_cpu_suspend)
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@ save registers on stack
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stmfd sp!, {r0 - r12, lr}
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@ Drain write cache
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mov r4, #0
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mcr p15, 0, r0, c7, c10, 4
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nop
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@ Load base address of Traffic Controller
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mov r6, #TCMIF_ASM_BASE & 0xff000000
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orr r6, r6, #TCMIF_ASM_BASE & 0x00ff0000
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orr r6, r6, #TCMIF_ASM_BASE & 0x0000ff00
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@ Prepare to put SDRAM into self-refresh manually
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ldr r7, [r6, #EMIFF_SDRAM_CONFIG_ASM_OFFSET & 0xff]
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orr r9, r7, #SELF_REFRESH_MODE & 0xff000000
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orr r9, r9, #SELF_REFRESH_MODE & 0x000000ff
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str r9, [r6, #EMIFF_SDRAM_CONFIG_ASM_OFFSET & 0xff]
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@ Prepare to put EMIFS to Sleep
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ldr r8, [r6, #EMIFS_CONFIG_ASM_OFFSET & 0xff]
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orr r9, r8, #IDLE_EMIFS_REQUEST & 0xff
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str r9, [r6, #EMIFS_CONFIG_ASM_OFFSET & 0xff]
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@ Load base address of ARM_IDLECT1 and ARM_IDLECT2
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mov r4, #CLKGEN_REG_ASM_BASE & 0xff000000
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orr r4, r4, #CLKGEN_REG_ASM_BASE & 0x00ff0000
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orr r4, r4, #CLKGEN_REG_ASM_BASE & 0x0000ff00
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@ Turn off clock domains
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@ Do not disable PERCK (0x04)
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mov r5, #OMAP1610_IDLECT2_SLEEP_VAL & 0xff
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orr r5, r5, #OMAP1610_IDLECT2_SLEEP_VAL & 0xff00
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strh r5, [r4, #ARM_IDLECT2_ASM_OFFSET & 0xff]
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@ Request ARM idle
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mov r3, #OMAP1610_IDLECT1_SLEEP_VAL & 0xff
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orr r3, r3, #OMAP1610_IDLECT1_SLEEP_VAL & 0xff00
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strh r3, [r4, #ARM_IDLECT1_ASM_OFFSET & 0xff]
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/*
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* Let's wait for the next wake up event to wake us up. r0 can't be
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* used here because r0 holds ARM_IDLECT1
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*/
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mov r2, #0
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mcr p15, 0, r2, c7, c0, 4 @ wait for interrupt
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@ Errata (HEL3SU467, section 1.4.4) specifies nop-instructions
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@ according to this formula:
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@ 2 + (4*DPLL_MULT)/DPLL_DIV/ARMDIV
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@ Max DPLL_MULT = 18
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@ DPLL_DIV = 1
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@ ARMDIV = 1
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@ => 74 nop-instructions
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop @10
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop @20
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop @30
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop @40
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop @50
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop @60
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop @70
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nop
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nop
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nop
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nop @74
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/*
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* omap1610_cpu_suspend()'s resume point.
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*
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* It will just start executing here, so we'll restore stuff from the
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* stack.
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*/
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@ Restore the ARM_IDLECT1 and ARM_IDLECT2.
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strh r1, [r4, #ARM_IDLECT2_ASM_OFFSET & 0xff]
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strh r0, [r4, #ARM_IDLECT1_ASM_OFFSET & 0xff]
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@ Restore EMIFF controls
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str r7, [r6, #EMIFF_SDRAM_CONFIG_ASM_OFFSET & 0xff]
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str r8, [r6, #EMIFS_CONFIG_ASM_OFFSET & 0xff]
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@ Restore regs and return
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ldmfd sp!, {r0 - r12, pc}
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ENTRY(omap1610_cpu_suspend_sz)
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.word . - omap1610_cpu_suspend
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#endif /* CONFIG_ARCH_OMAP16XX */
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