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0004952242
Random read/write errors are a bad thing - so don't let anyone (including the test bench) run on something we know is bad. Signed-off-by: Robin Getz <rgetz@blackfin.uclinux.org> Signed-off-by: Bryan Wu <cooloney@kernel.org>
76 lines
2.6 KiB
C
76 lines
2.6 KiB
C
/*
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* File: arch/blackfin/mach-common/arch_checks.c
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* Based on:
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* Author: Robin Getz <rgetz@blackfin.uclinux.org>
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*
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* Created: 25Jul07
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* Description: Do some checking to make sure things are OK
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*
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* Modified:
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* Copyright 2004-2007 Analog Devices Inc.
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*
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* Bugs: Enter bugs at http://blackfin.uclinux.org/
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see the file COPYING, or write
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* to the Free Software Foundation, Inc.,
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* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <asm/fixed_code.h>
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#include <mach/anomaly.h>
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#include <asm/clocks.h>
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#ifdef CONFIG_BFIN_KERNEL_CLOCK
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# if (CONFIG_VCO_HZ > CONFIG_MAX_VCO_HZ)
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# error "VCO selected is more than maximum value. Please change the VCO multipler"
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# endif
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# if (CONFIG_SCLK_HZ > CONFIG_MAX_SCLK_HZ)
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# error "Sclk value selected is more than maximum. Please select a proper value for SCLK multiplier"
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# endif
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# if (CONFIG_SCLK_HZ < CONFIG_MIN_SCLK_HZ)
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# error "Sclk value selected is less than minimum. Please select a proper value for SCLK multiplier"
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# endif
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# if (ANOMALY_05000273) && (CONFIG_SCLK_HZ * 2 > CONFIG_CCLK_HZ)
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# error "ANOMALY 05000273, please make sure CCLK is at least 2x SCLK"
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# endif
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# if (CONFIG_SCLK_HZ > CONFIG_CCLK_HZ) && (CONFIG_SCLK_HZ != CONFIG_CLKIN_HZ) && (CONFIG_CCLK_HZ != CONFIG_CLKIN_HZ)
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# error "Please select sclk less than cclk"
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# endif
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#endif /* CONFIG_BFIN_KERNEL_CLOCK */
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#if CONFIG_BOOT_LOAD < FIXED_CODE_END
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# error "The kernel load address must be after the fixed code section"
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#endif
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#if (CONFIG_BOOT_LOAD & 0x3)
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# error "The kernel load address must be 4 byte aligned"
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#endif
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/* The entire kernel must be able to make a 24bit pcrel call to start of L1 */
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#if ((0xffffffff - L1_CODE_START + 1) + CONFIG_BOOT_LOAD) > 0x1000000
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# error "The kernel load address is too high; keep it below 10meg for safety"
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#endif
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#ifdef ANOMALY_05000448
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# if ANOMALY_05000448
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# error You are using a part with anomaly 05000448, this issue causes random memory read/write failures - that means random crashes.
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# endif
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#endif
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