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b9cc98697d
The hardware automatically disables further interrupts after each event until rearmed. This allows a delay to be injected between the occurence of the interrupt and the running of the cleanup routine. The delay is scaled by the descriptor backlog and then written to the INTRDELAY register which specifies the number of microseconds to hold off interrupt delivery after an interrupt event occurs. According to powertop this reduces the interrupt rate from ~5000 intr/s to ~150 intr/s per without affecting throughput (simple dd to a raid6 array). Signed-off-by: Dan Williams <dan.j.williams@intel.com> |
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ioat | ||
ipu | ||
ppc4xx | ||
at_hdmac_regs.h | ||
at_hdmac.c | ||
coh901318_lli.c | ||
coh901318_lli.h | ||
coh901318.c | ||
dmaengine.c | ||
dmatest.c | ||
dw_dmac_regs.h | ||
dw_dmac.c | ||
fsldma.c | ||
fsldma.h | ||
iop-adma.c | ||
iovlock.c | ||
Kconfig | ||
Makefile | ||
mpc512x_dma.c | ||
mv_xor.c | ||
mv_xor.h | ||
shdma.c | ||
shdma.h | ||
txx9dmac.c | ||
txx9dmac.h |